Energy reduction in 3D NoCs through communication optimization

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dc.citation.epage609en_US
dc.citation.issueNumber6en_US
dc.citation.spage593en_US
dc.citation.volumeNumber97en_US
dc.contributor.authorOzturk, O.en_US
dc.contributor.authorAkturk I.en_US
dc.contributor.authorKadayif I.en_US
dc.contributor.authorTosun, S.en_US
dc.date.accessioned2016-02-08T09:50:01Z
dc.date.available2016-02-08T09:50:01Z
dc.date.issued2015en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.description.abstractNetwork-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.en_US
dc.identifier.doi10.1007/s00607-013-0378-1en_US
dc.identifier.issn0010-485X
dc.identifier.urihttp://hdl.handle.net/11693/21703
dc.language.isoEnglishen_US
dc.publisherSpringer Wienen_US
dc.relation.isversionofhttp://dx.doi.org/10.1007/s00607-013-0378-1en_US
dc.source.titleComputing : archives for scientific computingen_US
dc.subject3Den_US
dc.subjectNoCen_US
dc.subjectCommunicationen_US
dc.subjectComputer architectureen_US
dc.subjectEnergy utilizationen_US
dc.subjectNetwork architectureen_US
dc.subjectNetworks (circuits)en_US
dc.subjectVLSI circuitsen_US
dc.subjectBetter performanceen_US
dc.subjectCommunication optimizationen_US
dc.subjectEnergyen_US
dc.subjectNetwork-on-chip architecturesen_US
dc.subjectNoC architecturesen_US
dc.subjectSimulation parametersen_US
dc.subjectThree-dimensional (3D) integrated circuitsen_US
dc.subjectNetwork-on-chipen_US
dc.titleEnergy reduction in 3D NoCs through communication optimizationen_US
dc.typeArticleen_US
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