A two phase successive cancellation decoder architecture for polar codes

Simple item page
dc.citation.epage961en_US
dc.citation.spage957en_US
dc.contributor.authorPamuk, Alptekinen_US
dc.contributor.authorArıkan, Erdalen_US
dc.coverage.spatialIstanbul, Turkeyen_US
dc.date.accessioned2016-02-08T12:04:00Z
dc.date.available2016-02-08T12:04:00Z
dc.date.issued2013en_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.descriptionDate of Conference: 7-12 July 2013en_US
dc.description.abstractWe propose a two-phase successive cancellation (TPSC) decoder architecture for polar codes that exploits the array-code property of polar codes by breaking the decoding of a length-TV polar code into a series of length-√ L decoding cycles. Each decoding cycle consists of two phases: a first phase for decoding along the columns and a second phase for decoding along the rows of the code array. The reduced decoder size makes it more affordable to implement the core decoder logic using distributed memory elements consisting of flip-flops (FFs), as opposed to slower random access memory (RAM), leading to a speed up in clock frequency. To minimize the circuit complexity, a single decoder unit is used in both phases with minor modifications. The re-use of the same decoder module makes it necessary to recall certain internal decoder state variables between decoding cycles. Instead of storing the decoder state variables in RAM, the decoder discards them and calculates them again when needed. Overall, the decoder has O(√ L) circuit complexity excluding RAM, and a latency of approximately 2.57V. A RAM of size O(N) is needed for storing the channel log-likelihood variables and the decoder decision variables. As an example of the proposed method, a length N = 214 bit polar code is implemented in an FPGA and the synthesis results are compared with a previously reported FPGA implementation. The results show that the proposed architecture has lower complexity, lower memory utilization with higher throughput, and a clock frequency that is less sensitive to code length. © 2013 IEEE.en_US
dc.identifier.doi10.1109/ISIT.2013.6620368en_US
dc.identifier.issn2157-8095
dc.identifier.urihttp://hdl.handle.net/11693/27890
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ISIT.2013.6620368en_US
dc.source.title2013 IEEE International Symposium on Information Theoryen_US
dc.subjectError correcting codesen_US
dc.subjectDecoder architectureen_US
dc.subjectDecoding complexityen_US
dc.subjectError correcting codeen_US
dc.subjectPolar codesen_US
dc.subjectProposed architecturesen_US
dc.subjectRandom access memoryen_US
dc.subjectSuccessive cancellationen_US
dc.subjectSuccessive-cancellation decodingen_US
dc.subjectClocksen_US
dc.subjectInformation theoryen_US
dc.subjectRandom access storageen_US
dc.subjectDecodingen_US
dc.titleA two phase successive cancellation decoder architecture for polar codesen_US
dc.typeConference Paperen_US
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
A two phase successive cancellation decoder architecture for polar codes.pdf
Size:
152.73 KB
Format:
Adobe Portable Document Format
Description:
Full printable version
Download
Collections
Department of Electrical and Electronics Engineering