Scratch-pad memory based custom processor design for graph applications
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As more and more domains have started to process ever-growing graphs, the importance of graph analytics applications became more apparent. However, general-purpose processors are challenged to deal with the large memory footprint and the associated random memory accesses in graph applications, directing researchers towards domain-specific solutions. In this dissertation, we present a custom RISC-V graph processor that tries to increase the performance of graph applications by reducing the memory accesses. The novelty of the graph processor lies in the design of our software-controlled scratch-pad memories: Edge ScratchPad (ESP), Vertex Scratch-Pad (VSP), and Global Scratch-Pad (GSP). While ESP is preloaded with the edge data in parallel with the execution, VSP relieves the vertex traffic by reducing the conflicts caused by the vertex-related memory accesses. GSP takes over the load of the rest of the memory accesses as these three SPMs replace the conventional caches found in general-purpose systems. For the software to control this new functionality embedded in the graph processor, we extended RISC-V instruction set architecture with custom SPM-related instructions. We provided compiler support for the instructions and we modified the widely used PageRank, Single-Source Shortest Path, and Breadth-First Search algorithms in graph processor fashion to demonstrate the software-hardware interaction needed for the design. The experimental results on these applications show that the graph processor makes 18% to 72% less datapath-blocking memory accesses compared to a general-purpose processor based on the same RISC-V core.
KeywordsIterative graph applications
Instruction set architecture