| dc.contributor.author | Aktürk, İ. | en_US |
| dc.contributor.author | Öztürk, Özcan | en_US |
| dc.date.accessioned | 2020-02-03T08:03:10Z | |
| dc.date.available | 2020-02-03T08:03:10Z | |
| dc.date.issued | 2019 | |
| dc.identifier.issn | 0885-7458 | |
| dc.identifier.uri | http://hdl.handle.net/11693/52984 | |
| dc.description.abstract | The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized. A novel multi-metric scoring scheme is used which specifies L1 cache access characteristics of threads. Scheduling decisions are made based on these multi-metric scores of threads. | en_US |
| dc.language.iso | English | en_US |
| dc.source.title | International Journal of Parallel Programming | en_US |
| dc.relation.isversionof | https://dx.doi.org/10.1007/s10766-019-00637-y | en_US |
| dc.subject | Adaptive scheduling | en_US |
| dc.subject | Chip multiprocessors | en_US |
| dc.subject | Inter-thread contention | en_US |
| dc.subject | Multi-metric scoring | en_US |
| dc.title | Adaptive thread scheduling in chip multiprocessors | en_US |
| dc.type | Article | en_US |
| dc.department | Department of Computer Engineering | en_US |
| dc.citation.spage | 1014 | en_US |
| dc.citation.epage | 1044 | en_US |
| dc.citation.volumeNumber | 47 | en_US |
| dc.citation.issueNumber | 5-6 | en_US |
| dc.identifier.doi | 10.1007/s10766-019-00637-y | en_US |
| dc.publisher | Springer | en_US |
| dc.contributor.bilkentauthor | Öztürk, Özcan | |
