Application mapping algorithms for mesh-based network-on-chip architectures
Date
2015-03Source Title
Journal of Supercomputing : an international journal of high-performance computer design, analysis and use
Print ISSN
0920-8542
Electronic ISSN
1573-0484
Publisher
Springer New York LLC
Volume
71
Issue
3
Pages
995 - 1017
Language
English
Type
ArticleItem Usage Stats
115
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105
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Abstract
Due to shrinking technology sizes, more and more processing elements and
memory blocks are being integrated on a single die. However, traditional communication infrastructures (e.g., bus or point-to-point) cannot handle the synchronization
problems of these large systems. Using network-on-chip (NoC) is a step towards solving this communication problem. Energy- and communication-efficient application
mapping is a previously studied problem for mesh-based NoC architectures; however,
there is still need for intelligent mapping algorithms since current algorithms either
take too much running time or do not determine accurate results. To fill this need, in
this study, we propose two mapping algorithms (one based on simulated annealing
and one based on genetic algorithm) for energy- and communication-aware mapping
problems of mesh-based NoC architectures. We compare these two algorithms with
an integer linear programming-based method and a heuristic method using several
multimedia and synthetic benchmarks.
Keywords
NoCMesh topology
Mapping
Genetic algorithm
Simulated annealing
Integer linear programming
Heuristics