A template-based design methodology for graph-parallel hardware accelerators
Author
Ayupov, A.
Yesil, S.
Ozdal, M. M.
Kim, T.
Burns, S.
Ozturk, O.
Date
2017-05-19Source Title
IEEE Council on Electronic Design Automation
Print ISSN
0278-0070
Publisher
IEEE
Volume
37
Issue
2
Pages
420 - 430
Language
English
Type
ArticleItem Usage Stats
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Abstract
Graph applications have been gaining importance in the last decade due to emerging big data analytics problems such as Web graphs, social networks, and biological networks. For these applications, traditional CPU and GPU architectures suffer in terms of performance and power consumption due to irregular communications, random memory accesses, and load balancing problems. It has been shown that specialized hardware accelerators can achieve much better power and energy efficiency compared to the general purpose CPUs and GPUs. In this paper, we present a template-based methodology specifically targeted for hardware accelerator design of big-data graph applications. Important architectural features that are key for energy efficient execution are implemented in a common template. The proposed template-based methodology is used to design hardware accelerators for different graph applications with little effort. Compared to an application-specific high-level synthesis methodology, we show that the proposed methodology can generate hardware accelerators with up to 18× better energy efficiency and requires less design effort.