FPGA implementation of a fault-tolerant application-specific NoC design
2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)
Institute of Electrical and Electronics Engineers Inc.
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Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.
Field programmable gate arrays (FPGA)
Application specific network on chip
Fault tolerant design
Integrated circuit design
Published Version (Please cite this version)http://dx.doi.org/10.1109/DTIS.2016.7483876
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