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      A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model

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      Author(s)
      Onsori, Salman
      Asad, Arghavan
      Raahemifar, K.
      Fathy, M.
      Date
      2015-11
      Source Title
      ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)
      Publisher
      IEEE
      Pages
      261 - 262
      Language
      English
      Type
      Conference Paper
      Item Usage Stats
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      223
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      Abstract
      In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE.
      Keywords
      Convex-optimization
      Embedded chip-multiprocessor (eCMP)
      Hybrid memory architecture
      Non-volatile memory (NVM)
      Adaptive systems
      Convex optimization
      Data storage equipment
      Design
      Digital storage
      Multiprocessing systems
      Optimization
      Product design
      Programmable logic controllers
      Random access storage
      Static random access storage
      Convex modeling
      Embedded chips
      Energy delay product
      Memory design
      Memory layers
      Non-volatile memory
      Power constraints
      Proposed architectures
      Memory architecture
      Permalink
      http://hdl.handle.net/11693/37719
      Published Version (Please cite this version)
      http://dx.doi.org/10.1109/ISOCC.2015.7401747
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