A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model
ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)
261 - 262
Item Usage Stats
MetadataShow full item record
In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE.
Embedded chip-multiprocessor (eCMP)
Hybrid memory architecture
Non-volatile memory (NVM)
Data storage equipment
Programmable logic controllers
Random access storage
Static random access storage
Energy delay product
Published Version (Please cite this version)http://dx.doi.org/10.1109/ISOCC.2015.7401747
Showing items related by title, author, creator and subject.
Ozturk, O.; Kandemir, M.; Irwin, M. J. (Institute of Electrical and Electronics Engineers, 2009-06)The memory system presents one of the critical challenges in embedded system design and optimization. This is mainly due to the ever-increasing code complexity of embedded applications and the exponential increase seen in ...
Ozturk, O.; Kandemir, M.; Irwin, M. J. (The Institution of Engineering and Technology, 2010)One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the ...
Diouf, B.; Hantaş, C.; Cohen, A.; Özturk, Ö.; Palsberg, J. (Association for Computing Machinery, 2013)Compilers use software-controlled local memories to provide fast, predictable, and power-efficient access to critical data. We show that the local memory allocation for straight-line, or linearized programs is equivalent ...