OptMem: dark-silicon aware low latency hybrid memory design
2016 International Conference on VLSI Systems, Architectures, Technology and Applications, VLSI-SATA 2016
Institute of Electrical and Electronics Engineers Inc.
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In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-Transfer torque magnetic random-Access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design. © 2016 IEEE.
Embedded chip-multiprocessor (eCMP)
Hybrid memory architecture
Non-volatile memory (NVM)
Data storage equipment
Integrated circuit design
Static random access storage
Random access storage
Published Version (Please cite this version)http://dx.doi.org/10.1109/VLSI-SATA.2016.7593059
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