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dc.contributor.authorAhangari, H.en_US
dc.contributor.authorAlouani, I.en_US
dc.contributor.authorOzturk, O.en_US
dc.contributor.authorNiar, S.en_US
dc.date.accessioned2018-04-12T11:45:50Z
dc.date.available2018-04-12T11:45:50Z
dc.date.issued2017en_US
dc.identifier.isbn9781509067626
dc.identifier.issn2159-3469
dc.identifier.urihttp://hdl.handle.net/11693/37617
dc.description.abstractIn this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel self-correcting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output. © 2017 IEEE.en_US
dc.language.isoEnglishen_US
dc.source.titleProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSIen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ISVLSI.2017.82en_US
dc.subjectFlip-flopen_US
dc.subjectFPGAen_US
dc.subjectHardeningen_US
dc.subjectReconfigurabilityen_US
dc.subjectReliabilityen_US
dc.subjectStatic latchen_US
dc.subjectComputer control systemsen_US
dc.subjectEconomic and social effectsen_US
dc.subjectFault tolerant computer systemsen_US
dc.subjectField programmable gate arrays (FPGA)en_US
dc.subjectHardeningen_US
dc.subjectRadiation hardeningen_US
dc.subjectReconfigurable hardwareen_US
dc.subjectReliabilityen_US
dc.subjectVLSI circuitsen_US
dc.subjectMultiple bit upseten_US
dc.subjectReconfigurabilityen_US
dc.subjectReconfigurable devicesen_US
dc.subjectReconfigurable structureen_US
dc.subjectSingle event upsetsen_US
dc.subjectSstatic latchen_US
dc.subjectThree orders of magnitudeen_US
dc.subjectTriple modular redundancyen_US
dc.titleReconfigurable hardened latch and flip-flop for FPGAsen_US
dc.typeConference Paperen_US
dc.departmentDepartment of Computer Engineering
dc.citation.spage433en_US
dc.citation.epage438en_US
dc.identifier.doi10.1109/ISVLSI.2017.82en_US
dc.publisherIEEE Computer Societyen_US


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