Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy
Date
2017Source Title
Microprocessors and Microsystems
Print ISSN
0141-9331
Publisher
Elsevier BV
Volume
51
Pages
76 - 98
Language
English
Type
ArticleItem Usage Stats
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Abstract
Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, addressing dark silicon challenges in uncore component designs such as cache hierarchy, on-chip interconnect etc. that consume significant portion of the on-chip power consumption is largely unexplored. In this paper, for the first time, we propose an integrated approach which considers the impact of power consumption of core and uncore components simultaneously to improve multi/many-core performance in the dark silicon era. The proposed approach dynamically (1) predicts the changing program behavior on each core; (2) re-determines frequency/voltage, cache capacity and technology in each level of the cache hierarchy based on the program's scalability in order to satisfy the power and temperature constraints. In the proposed architecture, for future chip-multiprocessors (CMPs), we exploit emerging technologies such as non-volatile memories (NVMs) and 3D techniques to combat dark silicon. Also, for the first time, we propose a detailed power model which is useful for future dark silicon CMPs power modeling. Experimental results on SPEC 2000/2006 benchmarks show that the proposed method improves throughput by about 54.3% and energy-delay product by about 61% on average, respectively, in comparison with the conventional CMP architecture with homogenous cache system. (A preliminary short version of this work was presented in the 18th Euromicro Conference on Digital System Design (DSD), 2015.) © 2017 Elsevier B.V.
Keywords
Chip-multiprocessor (CMP)Dark-silicon
Hybrid cache hierarchy
Network-on-chip (NoC)
Non-volatile memory (NVM)
Optimization
Reconfigurable cache
Adaptive systems
Cache memory
Data storage equipment
Digital storage
Electric power utilization
Multiprocessing systems
Network architecture
Network-on-chip
Silicon
Systems analysis
Three dimensional integrated circuits
Chip multiprocessors
Hybrid caches
Reconfigurable
Integrated circuit design