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      Graph analytics accelerators for cognitive systems

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      Author(s)
      Ozdal, M. M.
      Yesil, S.
      Kim, T.
      Ayupov, A.
      Greth, J.
      Burns, S.
      Ozturk, O.
      Date
      2017
      Source Title
      IEEE Micro
      Print ISSN
      0272-1732
      Publisher
      Institute of Electrical and Electronics Engineers
      Volume
      37
      Issue
      1
      Pages
      42 - 51
      Language
      English
      Type
      Article
      Item Usage Stats
      221
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      323
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      Abstract
      Hardware accelerators are known to be performance and power efficient. This article focuses on accelerator design for graph analytics applications, which are commonly used kernels for cognitive systems. The authors propose a templatized architecture that is specifically optimized for vertex-centric graph applications with irregular memory access patterns, asynchronous execution, and asymmetric convergence. The proposed architecture addresses the limitations of existing CPU and GPU systems while providing a customizable template. The authors' experiments show that the generated accelerators can outperform a high-end CPU system with up to 3 times better performance and 65 times better power efficiency. © 1981-2012 IEEE.
      Keywords
      Parallel architectures
      Special-purpose and application-based systems
      Memory architecture
      Accelerator design
      Asynchronous executions
      Graph analytics
      Hardware accelerators
      Memory access patterns
      Power efficiency
      Power efficient
      Proposed architectures
      Cognitive systems
      Permalink
      http://hdl.handle.net/11693/37114
      Published Version (Please cite this version)
      http://dx.doi.org/10.1109/MM.2017.7
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      • Department of Computer Engineering 1510
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