High throughput decoding methods and architectures for polar codes with high energy-efficiency and low latency
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Polar coding is a low-complexity channel coding method that can provably achieve Shannon’s channel capacity for any binary-input discrete memoryless channels (B-DMC). Apart from the theoretical interest in the subject, polar codes have attracted attention for their potential applications. We propose high throughput and energy-efficient decoders for polar codes using combinational logic targeting, but not limited to, next generation communication services such as optical communications, Massive Machine-Type Communications (mMTC) and Terahertz communications. First, we propose a fully combinational logic architecture for Successive-Cancellation (SC) decoding, which is the basic decoding method for polar codes. The advantages of this architecture are high throughput, high energy-efficiency and flexibility. The proposed combinational SC decoder operates at very low clock frequencies compared to synchronous (sequential logic) decoders, but takes advantage of the high degree of parallelism inherent in such architectures to provide a higher throughput and higher energy-efficiency compared to synchronous implementations. We provide ASIC and FPGA implementation results to present the characteristics of the proposed architecture and show that the decoder achieves approximately 2.5 Gb/s throughput with a power consumption of 190 mW with 90 nm 1.3 V technology and block length of 1024. We also provide analytical estimates for complexity and combinational delay of such decoders. We explain the use of pipelining with combinational decoders and introduce pipelined combinational SC decoders. At longer block lengths, we propose a hybrid-logic SC decoder that combines the advantageous aspects of the combinational and synchronous decoders. In order to improve the throughput further, we use weighted majority-logic decoding for polar codes. Unlike SC decoding, majority-logic decoding fails to achieve channel capacity, but offers better throughput due its parallelizable schedule. We give a novel recursive description for weighted majority-logic decoding for bit-reversed polar codes and use the proposed definition for implementations without determining the check-sums individually as done in conventional majoritylogic decoding. We demonstrate by analytical estimates that the complexity and latency of the proposed architecture are O(Nlog2 3) and O(log2 2 N), respectively. Then, we validate the calculated estimates by a fully combinational logic implementation on ASIC. For a block length of 256, the implemented decoders achieve 17 Gb/s throughput with 90 nm 1.3 V technology. In order to compensate the error performance penalty of the majority-logic decoding, we propose novel hybrid decoders that combine SC and weighted majority-logic decoding algorithms. We demonstrate that very high latency gains can be obtained by such decoders with small error performance degradation with respect to SC decoding.
Error correcting codes
Successive cancellation decoder
Majority logic decoder