dc.contributor.advisor | Öztürk, Özcan | |
dc.contributor.author | Soltaniyeh, Mohammed Reza | |
dc.date.accessioned | 2016-07-20T12:27:38Z | |
dc.date.available | 2016-07-20T12:27:38Z | |
dc.date.copyright | 2015-07 | |
dc.date.issued | 2015-07 | |
dc.date.submitted | 2015-07-13 | |
dc.identifier.uri | http://hdl.handle.net/11693/30148 | |
dc.description | Cataloged from PDF version of article. | en_US |
dc.description | Thesis (M.S.): Bilkent University, Department of Computer Engineering, İhsan Doğramacı Bilkent University, 2015. | en_US |
dc.description | Includes bibliographical references (leaves 50-56). | en_US |
dc.description.abstract | Chip multiprocessors (CMPs) require effective cache coherence protocols as
well as fast virtual-to-physical address translation mechanisms for high performance.
Directory-based cache coherence protocols are the state-of-the-art approaches
in many-core CMPs to keep the data blocks coherent at the last level
private caches. However, the area overhead and high associativity requirement
of the directory structures may not scale well with increasingly higher number of
cores.
As shown in some prior studies, a significant percentage of data blocks are
accessed by only one core, therefore, it is not necessary to keep track of these in
the directory structure. In this thesis, we have two major contributions. First,
we showed that compared to the classification of cache blocks at page granularity
as done in some previous studies, data block classification at subpage level
helps to detect considerably more private data blocks. Consequently, it reduces
the percentage of blocks required to be tracked in the directory significantly
compared to similar page level classification approaches. This, in turn, enables
smaller directory caches with lower associativity to be used in CMPs without
hurting performance, thereby helping the directory structure to scale gracefully
with the increasing number of cores. Memory block classification at subpage level,
however, may increase the frequency of the operating system's involvement in updating
the maintenance bits belonging to subpages stored in page table entries,
nullifying some portion of performance benefits of subpage level data classification.
To overcome this, we propose as a second contribution, the distributed
on-chip page table. The proposed on-chip page table stores recently accessed pages in the system.
Our simulation results show that, our approach reduces the number of evictions
in directory caches by 58%, on the average. Moreover, system performance is
improved further by avoiding 84% of the references to OS page table through the
on-chip page table. | en_US |
dc.description.statementofresponsibility | by Mohammed Reza Soltaniyeh. | en_US |
dc.format.extent | viii, 56 leaves. | en_US |
dc.language.iso | English | en_US |
dc.rights | info:eu-repo/semantics/openAccess | en_US |
dc.subject | Cache Coherence Protocol | en_US |
dc.subject | Directory Cache | en_US |
dc.subject | Many-core Architecture | en_US |
dc.subject | Virtual-to-Physical Page Translation | en_US |
dc.subject | Page Table | en_US |
dc.title | Boosting performance of directory-based cache coherence protocols by detecting private memory blocks at subpage granularity and using a low cost on-chip page table | en_US |
dc.title.alternative | Özel blokların alt sayfa seviyesinde tespit edilmesi ve düşük maliyetli yonga üzeri sayfa tablo kullanılmasıyla dizin temelli önbellek tutarlığı verimliliğ inin artırılması | en_US |
dc.type | Thesis | en_US |
dc.department | Department of Computer Engineering | en_US |
dc.publisher | Bilkent University | en_US |
dc.description.degree | M.S. | en_US |
dc.identifier.itemid | B150878 | |
dc.embargo.release | 2017-01-01 | |