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      Process variation aware thread mapping for chip multiprocessors

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      Author
      Hong, S.
      Narayanan, S. H. K.
      Kandemir, M.
      Özturk, Özcan
      Date
      2009-04
      Source Title
      DATE '09 Proceedings of the Conference on Design, Automation and Test in Europe
      Publisher
      IEEE
      Pages
      821 - 826
      Language
      English
      Type
      Conference Paper
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      Abstract
      With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions. © 2009 EDAA.
      Keywords
      Cache latency
      Chip Multiprocessor
      Computational capability
      Experimental evidence
      Manufacturing technologies
      Mapping strategy
      Overall execution
      Peak frequencies
      Process variation
      Processor cores
      Runtimes
      Design
      Electric power utilization
      Microprocessor chips
      Multiprocessing systems
      Systems analysis
      Mapping
      Permalink
      http://hdl.handle.net/11693/28728
      Published Version (Please cite this version)
      https://doi.org/10.1109/DATE.2009.5090776
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      • Department of Computer Engineering 1370
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