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dc.contributor.authorNayfeh, A.en_US
dc.contributor.authorOkyay, Alien_US
dc.contributor.authorEl-Atab, N.en_US
dc.contributor.authorÖzcan, Ayşeen_US
dc.contributor.authorAlkış, Sabrien_US
dc.coverage.spatialCancun, Mexicoen_US
dc.date.accessioned2016-02-08T12:27:54Zen_US
dc.date.available2016-02-08T12:27:54Zen_US
dc.date.issued2014en_US
dc.identifier.issn1938-5862en_US
dc.identifier.urihttp://hdl.handle.net/11693/28718en_US
dc.descriptionDate of Conference: 5-9 October 2014en_US
dc.descriptionConference Name: 2014 ECS and SMEQ Joint International Meeting, 2014en_US
dc.description.abstractIn this work, a bottom-gate charge trapping memory device with Zinc-Oxide (ZnO) channel and 2-nm Si nanoparticles (Si-NPs) embedded in ZnO charge trapping layer is demonstrated. The active layers of the memory device are deposited by atomic layer deposition (ALD) and the Si-NPs are deposited by spin coating. The Si-NPs memory exhibits a threshold voltage (Vt) shift of 6.3 V at an operating voltage of -10/10 V while 2.6 V Vt shift is obtained without nanoparticles confirming that the Si-NPs act as energy states within the bandgap of the ZnO layer. In addition, a 3.4 V Vt is achieved at a very low operating voltage of -1 V/1 V due to the charging of the Si-NPs through Poole-Frenkel emission mechanism at an electric field across the tunnel oxide E > 0.36 MV/cm. The results highlight a promising technology for future ultra-low power memory devices.en_US
dc.language.isoEnglishen_US
dc.source.titleECS Transactionsen_US
dc.relation.isversionofhttp://dx.doi.org/10.1149/06417.0045ecsten_US
dc.subjectAtomic layer depositionen_US
dc.subjectElectric fieldsen_US
dc.subjectNanoparticlesen_US
dc.subjectThreshold voltageen_US
dc.subjectCharge trapping layersen_US
dc.subjectCharge trapping memoryen_US
dc.subjectLow operating voltageen_US
dc.subjectOperating voltageen_US
dc.subjectPoole-Frenkel emissionen_US
dc.subjectSi nanoparticlesen_US
dc.subjectSilicon nanoparticlesen_US
dc.subjectZinc oxide (ZnO)en_US
dc.titleLow power Zinc-Oxide based charge trapping memory with embedded silicon nanoparticlesen_US
dc.typeConference Paperen_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.departmentInstitute of Materials Science and Nanotechnology (UNAM)en_US
dc.citation.spage45en_US
dc.citation.epage49en_US
dc.citation.volumeNumber64en_US
dc.citation.issueNumber17en_US
dc.identifier.doi10.1149/06417.0045ecsten_US
dc.publisherECSen_US


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