A cache topology-aware multi-query scheduler for multicore architectures

Date
2014
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Source Title
IEEE International Symposium on Workload Characterization (IISWC)
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IEEE
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Pages
86 - 87
Language
English
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Abstract

Growing performance gap between processors and main memory has made it worthwhile to consider off-chip data accesses in multi-query processing [2], [1], [3]. Exploiting data-sharing opportunities among concurrent queries can be critical for effective utilization of the underlying shared memory hierarchy. Given a set of queries, there may be a common retrieval operation for several cases to the same data. A query can benefit from the data previously loaded into the shared cache/memory space by another query. However, if these queries are scheduled independently, it is very likely that the same data is brought from off-chip memory to on-chip caches multiple times, thereby consuming off-chip bandwidth and slowing down overall execution.

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Published Version (Please cite this version)