An ILP formulation for application mapping onto Network-on-Chips
Date
2009Source Title
2009 International Conference on Application of Information and Communication Technologies
Publisher
IEEE
Language
English
Type
Conference PaperItem Usage Stats
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Abstract
Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems suffer from signal propagation delays, signal integrity, and scalability. Network-on-Chip (NoC) is the biggest step towards the communication bottleneck of System-on-Chip (SoC) architectures. In this paper, we present an Integer Linear Programming (ILP) formulation for application mapping onto mesh based Network-on-Chips to minimize the energy consumption of the system. The proposed method obtains optimal or close to optimal results within the given computation time limit. We also experimentally investigate the impact of the size of the mesh architecture on the application mapping and total communication. ©2009 IEEE.
Keywords
Application mappingBus-based
Communication method
Computation time
Energy consumption
ILP formulation
Integer Linear Programming
Mesh architecture
Network on chip
Network-on-chips
Optimal results
Signal Integrity
Signal propagation delays
System-on-chip architecture
Application specific integrated circuits
Integer programming
Linearization
Mapping
Microprocessor chips
Optimization
Programmable logic controllers
Routers
VLSI circuits
Communication