• About
  • Policies
  • What is open access
  • Library
  • Contact
Advanced search
      View Item 
      •   BUIR Home
      • Scholarly Publications
      • Faculty of Engineering
      • Department of Computer Engineering
      • View Item
      •   BUIR Home
      • Scholarly Publications
      • Faculty of Engineering
      • Department of Computer Engineering
      • View Item
      JavaScript is disabled for your browser. Some features of this site may not work without it.

      An ILP formulation for application mapping onto Network-on-Chips

      Thumbnail
      View / Download
      248.2 Kb
      Author(s)
      Tosun, S.
      Öztürk, Özcan
      Ozen, M.
      Date
      2009
      Source Title
      2009 International Conference on Application of Information and Communication Technologies
      Publisher
      IEEE
      Language
      English
      Type
      Conference Paper
      Item Usage Stats
      169
      views
      203
      downloads
      Abstract
      Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems suffer from signal propagation delays, signal integrity, and scalability. Network-on-Chip (NoC) is the biggest step towards the communication bottleneck of System-on-Chip (SoC) architectures. In this paper, we present an Integer Linear Programming (ILP) formulation for application mapping onto mesh based Network-on-Chips to minimize the energy consumption of the system. The proposed method obtains optimal or close to optimal results within the given computation time limit. We also experimentally investigate the impact of the size of the mesh architecture on the application mapping and total communication. ©2009 IEEE.
      Keywords
      Application mapping
      Bus-based
      Communication method
      Computation time
      Energy consumption
      ILP formulation
      Integer Linear Programming
      Mesh architecture
      Network on chip
      Network-on-chips
      Optimal results
      Signal Integrity
      Signal propagation delays
      System-on-chip architecture
      Application specific integrated circuits
      Integer programming
      Linearization
      Mapping
      Microprocessor chips
      Optimization
      Programmable logic controllers
      Routers
      VLSI circuits
      Communication
      Permalink
      http://hdl.handle.net/11693/28661
      Published Version (Please cite this version)
      http://dx.doi.org/10.1109/ICAICT.2009.5372524
      Collections
      • Department of Computer Engineering 1435
      Show full item record

      Browse

      All of BUIRCommunities & CollectionsTitlesAuthorsAdvisorsBy Issue DateKeywordsTypeDepartmentsThis CollectionTitlesAuthorsAdvisorsBy Issue DateKeywordsTypeDepartments

      My Account

      LoginRegister

      Statistics

      View Usage StatisticsView Google Analytics Statistics

      Bilkent University

      If you have trouble accessing this page and need to request an alternate format, contact the site administrator. Phone: (312) 290 1771
      © Bilkent University - Library IT

      Contact Us | Send Feedback | Off-Campus Access | Admin | Privacy