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dc.contributor.authorAtak, Oğuzhanen_US
dc.contributor.authorAtalar, Abdullahen_US
dc.coverage.spatialRennes, France
dc.date.accessioned2016-02-08T12:23:45Z
dc.date.available2016-02-08T12:23:45Z
dc.date.issued2010-07en_US
dc.identifier.urihttp://hdl.handle.net/11693/28555
dc.descriptionDate of Conference: 7-9 July 2010
dc.descriptionConference name: ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors
dc.description.abstractThe mapping of high level applications onto the coarse grained reconfigurable architectures (CGRA) are usually performed manually by using graphical tools or when automatic compilation is used, some restrictions are imposed to the high level code. Since high level applications do not contain parallelism explicitly, mapping the application directly to CGRA is very difficult. In this paper, we present a middle level Language for Reconfigurable Computing (LRC). LRC is similar to assembly languages of microprocessors, with the difference that parallelism can be coded in LRC. LRC is an efficient language for describing control data flow graphs. Several applications such as FIR, multirate, multichannel filtering, FFT, 2D-IDCT, Viterbi decoding, UMTS and CCSDC turbo decoding, Wimax LDPC decoding are coded in LRC and mapped to the Bilkent Reconfigurable Computer with a performance (in terms of cycle count) close to that of ASIC implementations. The applicability of the computation model to a CGRA having low cost interconnection network has been validated by using placement and routing algorithms. © 2010 IEEE.en_US
dc.language.isoEnglishen_US
dc.source.titleProceedings of the International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2010en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ASAP.2010.5541009en_US
dc.subjectCoarse grained reconfigurable architecturesen_US
dc.subjectAssembly languageen_US
dc.subjectAutomatic compilationen_US
dc.subjectCoarse grained reconfigurable architectureen_US
dc.subjectComputation modelen_US
dc.subjectControl data flow graphsen_US
dc.subjectCycle counten_US
dc.subjectEfficient computationen_US
dc.subjectGraphical toolsen_US
dc.subjectHigh level applicationsen_US
dc.subjectLow costsen_US
dc.subjectMulti rateen_US
dc.subjectMulti-channel filteringen_US
dc.subjectPlacement and routingen_US
dc.subjectReconfigurable computeren_US
dc.subjectReconfigurable computingen_US
dc.subjectTurbo decodingen_US
dc.subjectViterbi decodingen_US
dc.subjectData flow analysisen_US
dc.subjectDecodingen_US
dc.subjectLinguisticsen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectNetwork architectureen_US
dc.subjectQuery languagesen_US
dc.subjectViterbi algorithmen_US
dc.subjectWimaxen_US
dc.subjectComputer architectureen_US
dc.titleAn efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computeren_US
dc.typeConference Paperen_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.citation.spage289en_US
dc.citation.epage292en_US
dc.identifier.doi10.1109/ASAP.2010.5541009en_US
dc.publisherIEEE
buir.contributor.orcidAtalar, Abdullah|0000-0002-1903-1240en_US


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