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      An efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computer

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      Author
      Atak, Oğuzhan
      Atalar, Abdullah
      Date
      2010-07
      Source Title
      Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2010
      Publisher
      IEEE
      Pages
      289 - 292
      Language
      English
      Type
      Conference Paper
      Item Usage Stats
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      Abstract
      The mapping of high level applications onto the coarse grained reconfigurable architectures (CGRA) are usually performed manually by using graphical tools or when automatic compilation is used, some restrictions are imposed to the high level code. Since high level applications do not contain parallelism explicitly, mapping the application directly to CGRA is very difficult. In this paper, we present a middle level Language for Reconfigurable Computing (LRC). LRC is similar to assembly languages of microprocessors, with the difference that parallelism can be coded in LRC. LRC is an efficient language for describing control data flow graphs. Several applications such as FIR, multirate, multichannel filtering, FFT, 2D-IDCT, Viterbi decoding, UMTS and CCSDC turbo decoding, Wimax LDPC decoding are coded in LRC and mapped to the Bilkent Reconfigurable Computer with a performance (in terms of cycle count) close to that of ASIC implementations. The applicability of the computation model to a CGRA having low cost interconnection network has been validated by using placement and routing algorithms. © 2010 IEEE.
      Keywords
      Coarse grained reconfigurable architectures
      Assembly language
      Automatic compilation
      Coarse grained reconfigurable architecture
      Computation model
      Control data flow graphs
      Cycle count
      Efficient computation
      Graphical tools
      High level applications
      Low costs
      Multi rate
      Multi-channel filtering
      Placement and routing
      Reconfigurable computer
      Reconfigurable computing
      Turbo decoding
      Viterbi decoding
      Data flow analysis
      Decoding
      Linguistics
      Microprocessor chips
      Network architecture
      Query languages
      Viterbi algorithm
      Wimax
      Computer architecture
      Permalink
      http://hdl.handle.net/11693/28555
      Published Version (Please cite this version)
      http://dx.doi.org/10.1109/ASAP.2010.5541009
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      • Department of Electrical and Electronics Engineering 3524
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