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dc.contributor.authorAktürk, İsmailen_US
dc.contributor.authorÖztürk, Özcanen_US
dc.coverage.spatialBelfast, UK
dc.date.accessioned2016-02-08T12:08:22Z
dc.date.available2016-02-08T12:08:22Z
dc.date.issued2013-02-03en_US
dc.identifier.urihttp://hdl.handle.net/11693/28014
dc.descriptionDate of Conference: 27 Feb.-1 March 2013
dc.descriptionConference name: 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013
dc.description.abstractNetwork-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. We explore how heterogeneous processors can be mapped onto the given 3D chip area to minimize the data access costs. Our initial results indicate that the proposed approach generates promising results within tolerable solution times. © 2013 IEEE.en_US
dc.language.isoEnglishen_US
dc.source.titleProceedings of the 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/PDP.2013.83en_US
dc.subject3Den_US
dc.subjectChip multiprocessoren_US
dc.subjectHeterogeneousen_US
dc.subjectNoCen_US
dc.subjectCommunication reductionen_US
dc.subjectHeterogeneousen_US
dc.subjectHeterogeneous processorsen_US
dc.subjectNetwork-on-chip architecturesen_US
dc.subjectThree dimensional integrated circuitsen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectRoutersen_US
dc.subjectVLSI circuitsen_US
dc.subjectThree dimensional computer graphicsen_US
dc.titleILP-based communication reduction for heterogeneous 3D network-on-chipsen_US
dc.typeConference Paperen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage514en_US
dc.citation.epage518en_US
dc.identifier.doi10.1109/PDP.2013.83en_US
dc.publisherIEEEen_US


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