ILP-based communication reduction for heterogeneous 3D network-on-chips
Author
Aktürk, İsmail
Öztürk, Özcan
Date
2013-02-03Source Title
Proceedings of the 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013
Publisher
IEEE
Pages
514 - 518
Language
English
Type
Conference PaperItem Usage Stats
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Abstract
Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. We explore how heterogeneous processors can be mapped onto the given 3D chip area to minimize the data access costs. Our initial results indicate that the proposed approach generates promising results within tolerable solution times. © 2013 IEEE.
Keywords
3DChip multiprocessor
Heterogeneous
NoC
Communication reduction
Heterogeneous
Heterogeneous processors
Network-on-chip architectures
Three dimensional integrated circuits
Microprocessor chips
Routers
VLSI circuits
Three dimensional computer graphics