A 128-bit microprocessor compatible programmable correlator chip for use in synchronous communication
Proceedings of the COMPEURO’89: VLSI and Computer Peripherals, IEEE 1989
146 - 147
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A single-chip microprocessor-compatible 128-b correlator is designed and implemented in a 3-μm M2CMOS process. Full-custom design techniques are applied to achieve the best tradeoff among chip size, speed, and power consumption. The chip is placed in a microprocessor-based portable data terminal using HF radio communication. It marks the beginning of a synchronous data stream received from the very noisy channel by detecing the synchronization (sync) word. The sync word can be detected for either inverted or noninverted input data streams. Two chips can be cascaded to make a 256-b correlator. The chip is fully programmable by a microprocessor to set the number of tolerable errors in detection and to select the bits of the 128-b (or 256-b) data stream to be used in the correlation.
Synchronous data streams