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dc.contributor.authorIshebabi H.en_US
dc.contributor.authorAscheid G.en_US
dc.contributor.authorMeyr H.en_US
dc.contributor.authorAtak, Oğuzhanen_US
dc.contributor.authorAtalar, Abdullahen_US
dc.contributor.authorArıkan, Erdalen_US
dc.coverage.spatialIsland of Kos, Greeceen_US
dc.date.accessioned2016-02-08T11:47:06Z
dc.date.available2016-02-08T11:47:06Z
dc.date.issued2006en_US
dc.identifier.issn0271-4310
dc.identifier.urihttp://hdl.handle.net/11693/27190
dc.descriptionDate of Conference: 21-24 May 2006en_US
dc.description.abstractFast Fourier Transformation (FFT) and it's inverse (IFFT) are used in Orthogonal Frequency Division Multiplexing (OFDM) systems for data (de)modulation. The transformations are the kernel tasks in an OFDM implementation, and are the most processing-intensive ones. Recent trends in the electronic consumer market require OFDM implementations to be flexible, making a trade-off between area, energy-efficiency, flexibility and timing a necessity. This has spurred the development of Application-Specific Instruction-Set Processors (ASIPs) for FFT processing. Parallelization is an architectural parameter that significantly influence design goals. This paper presents an analysis of the efficiency of parallelization techniques for an FFT-ASIP. It is shown that existing techniques are inefficient for high throughput applications such as Ultra Wideband (UWB), because of memory bottlenecks. Therefore, an interleaved execution technique which exploits temporal parallelism is proposed. With this technique, it is possible to meet the throughput requirement of UWB (409.6 Msamples/s) with only 4 non-trivial butterfly units for an ASIP that runs at 400MHz. © 2006 IEEE.en_US
dc.language.isoEnglishen_US
dc.source.title2006 IEEE International Symposium on Circuits and Systemsen_US
dc.subjectEnergy efficiencyen_US
dc.subjectFast Fourier transformsen_US
dc.subjectOrthogonal frequency division multiplexingen_US
dc.subjectParameter estimationen_US
dc.subjectProgram processorsen_US
dc.subjectApplication-Specific Instruction-Set Processors (ASIP)en_US
dc.subjectArchitectural parameteren_US
dc.subjectParallel processing systemsen_US
dc.titleAn efficient parallelization technique for high throughput FFT-ASIPsen_US
dc.typeConference Paperen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.citation.spage5664en_US
dc.citation.epage5667en_US
dc.publisherIEEEen_US


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