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dc.contributor.authorDuman, Kaanen_US
dc.contributor.authorÇoǧun, Fuaten_US
dc.contributor.authorÖktem, L.en_US
dc.coverage.spatialEskişehir, Turkeyen_US
dc.date.accessioned2016-02-08T11:43:31Z
dc.date.available2016-02-08T11:43:31Z
dc.date.issued2007en_US
dc.identifier.urihttp://hdl.handle.net/11693/27072
dc.descriptionDate of Conference: 11-13 June 2007en_US
dc.descriptionConference Name: 15th Signal Processing and Communications Applications, IEEE 2007en_US
dc.description.abstractA fully pipelined JPEG hardware accelerator that runs on FPGA is presented. The accelerator is designed interactively in a simulation environment, using a DSP hardware design automation tool chain. The encoder part of the accelerator accepts 8×8 image blocks in a streaming fashion, and outputs the zigzag-scanned, quantized 2-D DCT coefficients of the block. The decoder part accepts zigzag-scanned, quantized DCT coefficients, and outputs reconstructed 8×8 image block. Each part has a throughput of one system clock per pixel per channel. The encoder employs a fast pipelined implementation for 2-D DCT [1]. For the decoder, a new pipelined 2-D IDCT structure is developed. Our IDCT structure is based on an IDCT factorization for software implementation [2], and is inspired by the pipelined DCT structure employed in the encoder. The resource utilization and maximum frequency figures for a particular FPGA target suggest that our accelerator has competitive performance.en_US
dc.language.isoTurkishen_US
dc.source.titleProceedings of the 15th Signal Processing and Communications Applications, IEEE 2007en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/SIU.2007.4298563en_US
dc.subjectAccelerationen_US
dc.subjectClutchesen_US
dc.subjectComputer aided designen_US
dc.subjectCosine transformsen_US
dc.subjectDecodingen_US
dc.subjectDiscrete cosine transformsen_US
dc.subjectElectric fault locationen_US
dc.subjectField programmable gate arrays (FPGA)en_US
dc.subjectSignal processingen_US
dc.subjectCompetitive performanceen_US
dc.subjectDCT coefficientsen_US
dc.subjectDSP hardwareen_US
dc.subjectFully pipelineden_US
dc.subjectHardware acceleratorsen_US
dc.subjectIDCT structureen_US
dc.subjectImage blocksen_US
dc.subjectMaximum frequencyen_US
dc.subjectPipelined implementationen_US
dc.subjectQuantized DCT coefficientsen_US
dc.subjectResource utilizationsen_US
dc.subjectSimulation environmentsen_US
dc.subjectSoftware implementationsen_US
dc.subjectSystem clocksen_US
dc.subjectPipeline processing systemsen_US
dc.titleJPEG hardware accelerator design for FPGAen_US
dc.title.alternativeFPGA için JPEG donanımsal hızlandırıcı tasarımıen_US
dc.typeConference Paperen_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.identifier.doi10.1109/SIU.2007.4298563en_US
dc.publisherIEEEen_US


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