JPEG hardware accelerator design for FPGA
Author
Duman, Kaan
Çoǧun, Fuat
Öktem, L.
Date
2007Source Title
Proceedings of the 15th Signal Processing and Communications Applications, IEEE 2007
Print ISSN
2165-0608
Publisher
IEEE
Language
Turkish
Type
Conference PaperItem Usage Stats
162
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Abstract
A fully pipelined JPEG hardware accelerator that runs on FPGA is presented. The accelerator is designed interactively in a simulation environment, using a DSP hardware design automation tool chain. The encoder part of the accelerator accepts 8×8 image blocks in a streaming fashion, and outputs the zigzag-scanned, quantized 2-D DCT coefficients of the block. The decoder part accepts zigzag-scanned, quantized DCT coefficients, and outputs reconstructed 8×8 image block. Each part has a throughput of one system clock per pixel per channel. The encoder employs a fast pipelined implementation for 2-D DCT [1]. For the decoder, a new pipelined 2-D IDCT structure is developed. Our IDCT structure is based on an IDCT factorization for software implementation [2], and is inspired by the pipelined DCT structure employed in the encoder. The resource utilization and maximum frequency figures for a particular FPGA target suggest that our accelerator has competitive performance.
Keywords
Computer aided designCosine transforms
Discrete cosine transforms
Electric fault location
Field programmable gate arrays (FPGA)
Signal processing
DCT coefficients
DSP hardware
Fully pipelined
Hardware accelerators
IDCT structure
Image blocks
Pipelined implementation
Quantized DCT coefficients
Simulation environments
Software implementations
Pipeline processing systems