Show simple item record

dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.authorKandemir, M.en_US
dc.contributor.authorNarayanan, S. H. K.en_US
dc.coverage.spatialSan Jose, CA, USA
dc.date.accessioned2016-02-08T11:38:34Z
dc.date.available2016-02-08T11:38:34Z
dc.date.issued2008-03en_US
dc.identifier.urihttp://hdl.handle.net/11693/26881
dc.descriptionDate of Conference: 17-19 March 2008
dc.descriptionConference name: 9th International Symposium on Quality Electronic Design, ISQED 2008
dc.description.abstractExecuting array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, which distributes the iterations of a loop to be executed in parallel across the available processors. Most of the existing work in this area targets cache based execution platforms. In comparison, this paper proposes the first dynamic loop scheduler, to our knowledge, that targets scratch-pad memory (SPM) based chip multiprocessors, and presents an experimental evaluation of it. The main idea behind our approach is to identify the set of loop iterations that access the SPM and those that do not. This information is exploited at runtime to balance the loads of the processors involved in executing the loop nest at hand. Therefore, the proposed dynamic scheduler takes advantage of the SPM in performing the loop iteration-to-processor mapping. Our experimental evaluation with eight array/loop intensive applications reveals that the proposed scheduler is very effective in practice and brings between 13.7% and 41.7% performance savings over a static loop scheduling scheme, which is also tested in our experiments. © 2008 IEEE.en_US
dc.language.isoEnglishen_US
dc.source.titleProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ISQED.2008.4479830en_US
dc.subjectCode convertersen_US
dc.subjectData storage equipmenten_US
dc.subjectElectronics engineeringen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectProgram compilersen_US
dc.subjectSecurity of dataen_US
dc.subjectSelf phase modulationen_US
dc.subjectSingle point mooringen_US
dc.subjectStatistical process controlen_US
dc.subjectSystems analysisen_US
dc.subjectChip multi processoren_US
dc.subjectChip multi processorsen_US
dc.subjectCritical issuesen_US
dc.subjectDynamic loop schedulingen_US
dc.subjectDynamic Scheduleren_US
dc.subjectElectronic designsen_US
dc.subjectExperimental evaluationsen_US
dc.subjectInternational symposiumen_US
dc.subjectLoop iterationen_US
dc.subjectLoop schedulingen_US
dc.subjectOptimizing compilersen_US
dc.subjectParallelizationen_US
dc.subjectRun-timeen_US
dc.subjectScratch-pad memoriesen_US
dc.subjectScratch-pad memoryen_US
dc.subjectSchedulingen_US
dc.titleA scratch-pad memory aware dynamic loop scheduling algorithmen_US
dc.typeConference Paperen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage738en_US
dc.citation.epage743en_US
dc.identifier.doi10.1109/ISQED.2008.4479830en_US
dc.publisherIEEE


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record