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      A scratch-pad memory aware dynamic loop scheduling algorithm

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      Author
      Öztürk, Özcan
      Kandemir, M.
      Narayanan, S. H. K.
      Date
      2008-03
      Source Title
      Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
      Publisher
      IEEE
      Pages
      738 - 743
      Language
      English
      Type
      Conference Paper
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      Abstract
      Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, which distributes the iterations of a loop to be executed in parallel across the available processors. Most of the existing work in this area targets cache based execution platforms. In comparison, this paper proposes the first dynamic loop scheduler, to our knowledge, that targets scratch-pad memory (SPM) based chip multiprocessors, and presents an experimental evaluation of it. The main idea behind our approach is to identify the set of loop iterations that access the SPM and those that do not. This information is exploited at runtime to balance the loads of the processors involved in executing the loop nest at hand. Therefore, the proposed dynamic scheduler takes advantage of the SPM in performing the loop iteration-to-processor mapping. Our experimental evaluation with eight array/loop intensive applications reveals that the proposed scheduler is very effective in practice and brings between 13.7% and 41.7% performance savings over a static loop scheduling scheme, which is also tested in our experiments. © 2008 IEEE.
      Keywords
      Code converters
      Data storage equipment
      Electronics engineering
      Microprocessor chips
      Multiprocessing systems
      Program compilers
      Security of data
      Self phase modulation
      Single point mooring
      Statistical process control
      Systems analysis
      Chip multi processor
      Chip multi processors
      Critical issues
      Dynamic loop scheduling
      Dynamic Scheduler
      Electronic designs
      Experimental evaluations
      International symposium
      Loop iteration
      Loop scheduling
      Optimizing compilers
      Parallelization
      Run-time
      Scratch-pad memories
      Scratch-pad memory
      Scheduling
      Permalink
      http://hdl.handle.net/11693/26881
      Published Version (Please cite this version)
      http://dx.doi.org/10.1109/ISQED.2008.4479830
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      • Department of Computer Engineering 1368
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