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dc.contributor.authorDemirbas, D.en_US
dc.contributor.authorAkturk, I.en_US
dc.contributor.authorOzturk, O.en_US
dc.contributor.authorGüdükbay, Uğuren_US
dc.date.accessioned2016-02-08T11:01:53Z
dc.date.available2016-02-08T11:01:53Z
dc.date.issued2014en_US
dc.identifier.issn0010-4620
dc.identifier.urihttp://hdl.handle.net/11693/26583
dc.description.abstractAs a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in application-specific NoC design is to find the right balance among different tradeoffs, such as communication latency, power consumption and chip area. We propose a novel approach that generates latency-aware heterogeneous NoC topology. Experimental results show that our approach improves the total communication latency up to 27% with modest power consumption. © 2013 The Author 2013. Published by Oxford University Press on behalf of The British Computer Society.en_US
dc.language.isoEnglishen_US
dc.source.titleThe Computer Journalen_US
dc.relation.isversionofhttp://dx.doi.org/10.1093/comjnl/bxt011en_US
dc.subjectMany-core architecturesen_US
dc.subjectMultiprocessor system-on-chip designen_US
dc.subjectNetwork-on-chip synthesisen_US
dc.subjectComputer architectureen_US
dc.subjectHeterogeneous networksen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectRoutersen_US
dc.subjectVLSI circuitsen_US
dc.subjectChip multiprocessoren_US
dc.subjectCommunication latencyen_US
dc.subjectHeterogeneous NoCen_US
dc.titleApplication-specific heterogeneous network-on-chip designen_US
dc.typeArticleen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage1117en_US
dc.citation.epage1131en_US
dc.citation.volumeNumber57en_US
dc.citation.issueNumber8en_US
dc.identifier.doi10.1093/comjnl/bxt011en_US
dc.publisherOxford University Pressen_US
dc.contributor.bilkentauthorGüdükbay, Uğur


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