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      Two novel multiway circuit partitioning algorithms using relaxed locking

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      Author
      Dasdan, A.
      Aykanat, Cevdet
      Date
      1997
      Source Title
      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
      Print ISSN
      0278-0070
      Electronic ISSN
      1937-4151
      Publisher
      IEEE
      Volume
      16
      Issue
      2
      Pages
      169 - 178
      Language
      English
      Type
      Article
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      86
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      Abstract
      All the previous Kernighan-Lin-based (KL-based) circuit partitioning algorithms employ the locking mechanism, which enforces each cell to move exactly once per pass. In this paper, we propose two novel approaches for multiway circuit partitioning to overcome this limitation. Our approaches allow each cell to move more than once. Our first approach still uses the locking mechanism but in a relaxed way. It introduces the phase concept such that each pass can include more than one phase, and a phase can include at most one move of each cell. Our second approach does not use the locking mechanism at all. It introduces the mobility concept such that each cell can move as freely as allowed by its mobility. Each approach leads to KL-based generic algorithms whose parameters can be set to obtain algorithms with different performance characteristics. We generated three versions of each generic algorithm and evaluated them on a subset of common benchmark circuits in comparison with Sanchis' algorithm (FMS) and the simulated annealing algorithm (SA). Experimental results show that our algorithms are efficient, they outperform FMS significantly, and they perform comparably to SA. Our algorithms perform relatively better as the number of parts in the partition increases as well as the density of the circuit decreases. This paper also provides guidelines for good parameter settings for the generic algorithms. © 1997 IEEE.
      Keywords
      Iterative Improvement
      Kernighan-Lin-Based Algorithms
      Move-Based Partitioning
      Multiway Circuit Partitioning
      Relaxed Locking
      Very large scale integration (vlsi)
      Computer Aided Network Analysis
      Genetic Algorithms
      Iterative Methods
      Simulated Annealing
      VLSI Circuits
      Permalink
      http://hdl.handle.net/11693/25571
      Published Version (Please cite this version)
      http://dx.doi.org/10.1109/43.573831
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