Show simple item record

dc.contributor.authorAykanat, Cevdeten_US
dc.contributor.authorBultan, T.en_US
dc.contributor.authorHaritaoğlu, İ.en_US
dc.date.accessioned2016-02-08T10:43:45Z
dc.date.available2016-02-08T10:43:45Zen_US
dc.date.issued1998en_US
dc.identifier.issn0893-6080
dc.identifier.urihttp://hdl.handle.net/11693/25378en_US
dc.description.abstractCell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.en_US
dc.language.isoEnglishen_US
dc.source.titleNeural Networksen_US
dc.relation.isversionofhttp://dx.doi.org/10.1016/S0893-6080(98)00089-6en_US
dc.subjectCell Placement Problemen_US
dc.subjectField Programmable Gate Arrayen_US
dc.subjectMean Field Annealingen_US
dc.subjectNeural-Network Algorithmsen_US
dc.subjectVLSI Circuit Designen_US
dc.subjectField Programmable Gate Arraysen_US
dc.subjectIntegrated Circuit Layouten_US
dc.subjectLearning Algorithmsen_US
dc.subjectSimulated Annealingen_US
dc.subjectVLSI Circuitsen_US
dc.subjectCell Placement Problemsen_US
dc.subjectMean Field Annealing (MFA)en_US
dc.subjectFeedforward Neural Networksen_US
dc.subjectAlgorithmen_US
dc.subjectArticleen_US
dc.subjectArtificial Neural Networken_US
dc.subjectAutomationen_US
dc.subjectComputer Aided Designen_US
dc.subjectComputer Programen_US
dc.subjectComputer Simulationen_US
dc.subjectMathematical Computingen_US
dc.subjectPriority Journalen_US
dc.subjectProblem Solvingen_US
dc.titleA fast neural-network algorithm for VLSI cell placementen_US
dc.typeArticleen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage1671en_US
dc.citation.epage1684en_US
dc.citation.volumeNumber11en_US
dc.citation.issueNumber9en_US
dc.identifier.doi10.1016/S0893-6080(98)00089-6en_US
dc.publisherPergamon Pressen_US
dc.contributor.bilkentauthorAykanat, Cevdet
dc.identifier.eissn1879-2782


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record