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      A fast neural-network algorithm for VLSI cell placement

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      Author(s)
      Aykanat, Cevdet
      Bultan, T.
      Haritaoğlu, İ.
      Date
      1998
      Source Title
      Neural Networks
      Print ISSN
      0893-6080
      Electronic ISSN
      1879-2782
      Publisher
      Pergamon Press
      Volume
      11
      Issue
      9
      Pages
      1671 - 1684
      Language
      English
      Type
      Article
      Item Usage Stats
      203
      views
      202
      downloads
      Abstract
      Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.
      Keywords
      Cell Placement Problem
      Field Programmable Gate Array
      Mean Field Annealing
      Neural-Network Algorithms
      VLSI Circuit Design
      Field Programmable Gate Arrays
      Integrated Circuit Layout
      Learning Algorithms
      Simulated Annealing
      VLSI Circuits
      Cell Placement Problems
      Mean Field Annealing (MFA)
      Feedforward Neural Networks
      Algorithm
      Article
      Artificial Neural Network
      Automation
      Computer Aided Design
      Computer Program
      Computer Simulation
      Mathematical Computing
      Priority Journal
      Problem Solving
      Permalink
      http://hdl.handle.net/11693/25378
      Published Version (Please cite this version)
      http://dx.doi.org/10.1016/S0893-6080(98)00089-6
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      • Department of Computer Engineering 1510
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