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dc.contributor.authorOzturk, O.en_US
dc.date.accessioned2016-02-08T09:58:46Z
dc.date.available2016-02-08T09:58:46Z
dc.date.issued2010en_US
dc.identifier.issn0045-7906
dc.identifier.urihttp://hdl.handle.net/11693/22334
dc.description.abstractChip multiprocessors (CMPs) are promising candidates for the next generation computing platforms to utilize large numbers of gates and reduce the effects of high interconnect delays. One of the key challenges in CMP design is to balance out the often-conflicting demands. Specifically, for today's image/video applications and systems, power consumption, memory space occupancy, area cost, and reliability are as important as performance. Therefore, a compilation framework for CMPs should consider multiple factors during the optimization process. Motivated by this observation, this paper addresses the energy-aware reliability support for the CMP architectures, targeting in particular at array-intensive image/video applications. There are two main goals behind our compiler approach. First, we want to minimize the energy wasted in executing replicas when there is no error during execution (which should be the most frequent case in practice). Second, we want to minimize the time to recover (through the replicas) from an error when it occurs. This approach has been implemented and tested using four parallel array-based applications from the image/video processing domain. Our experimental evaluation indicates that the proposed approach saves significant energy over the case when all the replicas are run under the highest voltage/frequency level, without sacrificing any reliability over the latter. © 2009 Elsevier Ltd. All rights reserved.en_US
dc.language.isoEnglishen_US
dc.source.titleComputers & Electrical Engineering: an international journalen_US
dc.relation.isversionofhttp://dx.doi.org/10.1016/j.compeleceng.2009.11.004en_US
dc.subjectChip multiprocessorsen_US
dc.subjectCode replicationen_US
dc.subjectCompilersen_US
dc.subjectEnergy consumptionen_US
dc.subjectReliabilityen_US
dc.titleImproving chip multiprocessor reliability through code replicationen_US
dc.typeArticleen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage480en_US
dc.citation.epage490en_US
dc.citation.volumeNumber36en_US
dc.citation.issueNumber3en_US
dc.identifier.doi10.1016/j.compeleceng.2009.11.004en_US
dc.publisherPergamon Pressen_US


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