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dc.contributor.authorOzturk, O.en_US
dc.contributor.authorDemirbas, D.en_US
dc.date.accessioned2016-02-08T09:56:45Z
dc.date.available2016-02-08T09:56:45Z
dc.date.issued2010en_US
dc.identifier.issn0020-7217
dc.identifier.urihttp://hdl.handle.net/11693/22193
dc.description.abstractThis article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor exhibit different properties such as performance, energy, temperature, area and communication bandwidth. Focusing primarily on array-dominated applications and heterogeneous execution environments, the proposed approach tries to optimise the distribution of the nodes for a given NoC area under the constraints present in the environment. This article is the first one, to our knowledge, that explores the possibility of employing evolutionary computational techniques for optimally placing the heterogeneous nodes in an NoC. We also compare our approach with an optimal integer linear programming (ILP) approach using a commercial ILP tool. The results collected so far are very encouraging and indicate that the proposed approach generates close results to the ILP-based approach with minimal execution latencies. © 2010 Taylor & Francis.en_US
dc.language.isoEnglishen_US
dc.source.titleInternational Journal of Electronicsen_US
dc.relation.isversionofhttp://dx.doi.org/10.1080/00207217.2010.512020en_US
dc.subjectEvolutionary computingen_US
dc.subjectGenetic algorithmen_US
dc.subjectHeterogeneousen_US
dc.subjectNoCen_US
dc.subjectBiologically inspireden_US
dc.subjectChip multiprocessoren_US
dc.subjectCommunication bandwidthen_US
dc.subjectComputational techniqueen_US
dc.subjectExecution environmentsen_US
dc.subjectHeterogeneous nodesen_US
dc.subjectInteger linear programmingen_US
dc.subjectNetwork - on - chip architecturesen_US
dc.subjectNetwork - on - chip designen_US
dc.subjectHeterogeneous networksen_US
dc.subjectInteger programmingen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectOptimizationen_US
dc.subjectServersen_US
dc.subjectTelecommunication systemsen_US
dc.subjectVLSI circuitsen_US
dc.subjectGenetic algorithmsen_US
dc.titleHeterogeneous network-on-chip design through evolutionary computingen_US
dc.typeArticleen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage1139en_US
dc.citation.epage1161en_US
dc.citation.volumeNumber97en_US
dc.citation.issueNumber10en_US
dc.identifier.doi10.1080/00207217.2010.512020en_US
dc.publisherTaylor & Francisen_US
dc.identifier.eissn1362-3060


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