On-chip memory space partitioning for chip multiprocessors using polyhedral algebra
Irwin, M. J.
IET Computers and Digital Techniques
The Institution of Engineering and Technology
484 - 498
Item Usage Stats
MetadataShow full item record
One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same application. Here, two problems are formulated. First, we show how a polyhedral method can be used to design, for array-based data-intensive embedded applications, an application-specific hybrid memory architecture that has both shared and private components. We evaluate the resulting memory configurations using a set of benchmarks and compare them to pure private and pure shared memory on-chip multiprocessor architectures. The second approach proposed consider dynamic configuration of software-managed on-chip memory space to adapt to the runtime variations in data storage demand and interprocessor sharing patterns. The proposed framework is fully implemented using an optimising compiler, a polyhedral tool, and a memory partitioner (based on integer linear programming), and is tested using a suite of eight data-intensive embedded applications. © 2010 © The Institution of Engineering and Technology.
Integer linear programming
On chip memory
Published Version (Please cite this version)http://dx.doi.org/10.1049/iet-cdt.2009.0089
Showing items related by title, author, creator and subject.
Ozturk, O.; Kandemir, M.; Irwin, M. J. (Institute of Electrical and Electronics Engineers, 2009-06)The memory system presents one of the critical challenges in embedded system design and optimization. This is mainly due to the ever-increasing code complexity of embedded applications and the exponential increase seen in ...
Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M. (IEEE, 2015-11)In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories ...
Diouf, B.; Hantaş, C.; Cohen, A.; Özturk, Ö.; Palsberg, J. (Association for Computing Machinery, 2013)Compilers use software-controlled local memories to provide fast, predictable, and power-efficient access to critical data. We show that the local memory allocation for straight-line, or linearized programs is equivalent ...