On-chip memory space partitioning for chip multiprocessors using polyhedral algebra
Author
Ozturk, O.
Kandemir, M.
Irwin, M. J.
Date
2010Source Title
IET Computers and Digital Techniques
Print ISSN
1751-8601
Publisher
The Institution of Engineering and Technology
Volume
4
Issue
6
Pages
484 - 498
Language
English
Type
ArticleItem Usage Stats
133
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views
109
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downloads
Abstract
One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same application. Here, two problems are formulated. First, we show how a polyhedral method can be used to design, for array-based data-intensive embedded applications, an application-specific hybrid memory architecture that has both shared and private components. We evaluate the resulting memory configurations using a set of benchmarks and compare them to pure private and pure shared memory on-chip multiprocessor architectures. The second approach proposed consider dynamic configuration of software-managed on-chip memory space to adapt to the runtime variations in data storage demand and interprocessor sharing patterns. The proposed framework is fully implemented using an optimising compiler, a polyhedral tool, and a memory partitioner (based on integer linear programming), and is tested using a suite of eight data-intensive embedded applications. © 2010 © The Institution of Engineering and Technology.
Keywords
Application-specificChip multiprocessor
Data sharing
Data storage
Dynamic configuration
Embedded application
Hybrid memories
Integer linear programming
Interprocessor sharing
Memory architecture
Memory configuration
On chip memory
On-chip multiprocessor
Run-time variations
Shared memories
Integer programming
Microprocessor chips
Multiprocessing systems
Optimization
Systems analysis
Computer architecture
Permalink
http://hdl.handle.net/11693/22152Published Version (Please cite this version)
http://dx.doi.org/10.1049/iet-cdt.2009.0089Collections
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