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dc.contributor.authorOruc, F. B.en_US
dc.contributor.authorCimen, F.en_US
dc.contributor.authorRizk, A.en_US
dc.contributor.authorGhaffari, M.en_US
dc.contributor.authorNayfeh, A.en_US
dc.contributor.authorOkyay, A., K.en_US
dc.date.accessioned2016-02-08T09:43:43Z
dc.date.available2016-02-08T09:43:43Z
dc.date.issued2012-10-26en_US
dc.identifier.issn0741-3106
dc.identifier.urihttp://hdl.handle.net/11693/21253
dc.description.abstractA thin-film ZnO-based single-transistor memory cell with a gate stack deposited in a single atomic layer deposition step is demonstrated. Thin-film ZnO is used as channel material and charge-trapping layer for the first time. The extracted mobility and subthreshold slope of the thin-film device are 23 cm2/V · s and 720 mV/dec, respectively. The memory effect is verified by a 2.35-V hysteresis in the $I\rm drain- $V\rm gate curve. Physics-based TCAD simulations show very good agreement with the experimental results providing insight to the charge-trapping physics.en_US
dc.language.isoEnglishen_US
dc.source.titleIEEE Electron Device Lettersen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/LED.2012.2219493en_US
dc.subjectAtomic layer deposition (ALD)en_US
dc.subjectFlash memoryen_US
dc.subjectThin-film transistor (TFT)en_US
dc.subjectZnOen_US
dc.subjectChannel materialsen_US
dc.subjectCharge trapping memoriesen_US
dc.subjectGate stacksen_US
dc.subjectMemory cellen_US
dc.subjectMemory effectsen_US
dc.subjectPhysics-baseden_US
dc.subjectSubthreshold slopeen_US
dc.subjectTCAD simulationen_US
dc.subjectThin-film transistor (TFTs)en_US
dc.subjectZnOen_US
dc.subjectAtomic layer depositionen_US
dc.subjectFlash memoryen_US
dc.subjectSemiconductor storageen_US
dc.subjectThin film devicesen_US
dc.subjectZinc oxideen_US
dc.subjectThin film transistorsen_US
dc.titleThin-film ZnO charge-trapping memory cell grown in a single ALD stepen_US
dc.typeArticleen_US
dc.departmentDepartment of Electrical and Electronics Engineering
dc.departmentUNAM - Institute of Materials Science and Nanotechnology
dc.citation.spage1714en_US
dc.citation.epage1716en_US
dc.citation.volumeNumber33en_US
dc.citation.issueNumber12en_US
dc.identifier.doi10.1109/LED.2012.2219493en_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US


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