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dc.contributor.authorKadayif, I.en_US
dc.contributor.authorTurkcan, M.en_US
dc.contributor.authorKiziltepe, S.en_US
dc.contributor.authorOzturk, O.en_US
dc.date.accessioned2016-02-08T09:35:00Z
dc.date.available2016-02-08T09:35:00Z
dc.date.issued2013en_US
dc.identifier.issn1084-4309
dc.identifier.urihttp://hdl.handle.net/11693/20775
dc.description.abstractAs technology moves towards finer process geometries, it is becoming extremely difficult to control critical physical parameters such as channel length, gate oxide thickness, and dopant ion concentration. Variations in these parameters lead to dramatic variations in access latencies in Static Random Access Memory (SRAM) devices. This means that different lines of the same cache may have different access latencies. A simple solution to this problem is to adopt the worst-case latency paradigm. While this egalitarian cache management is simple, it may introduce significant performance overhead during instruction fetches when both address translation (instruction Translation Lookaside Buffer (TLB) access) and instruction cache access take place, making this solution infeasible for future high-performance processors. In this study, we first propose some hardware and software enhancements and then, based on those, investigate several techniques to mitigate the effect of process variation on the instruction fetch pipeline stage in modern processors. For address translation, we study an approach that performs the virtual-to-physical page translation once, then stores it in a special register, reusing it as long as the execution remains on the same instruction page. To handle varying access latencies across different instruction cache lines, we annotate the cache access latency of instructions within themselves to give the circuitry a hint about how long to wait for the next instruction to become available. © 2013 ACM.en_US
dc.language.isoEnglishen_US
dc.source.titleACM Transactions on Design Automation of Electronic Systemsen_US
dc.relation.isversionofhttp://dx.doi.org/10.1145/2489778en_US
dc.subjectAddress translationen_US
dc.subjectEncodingen_US
dc.subjectProcess variationen_US
dc.subjectInstruction cacheen_US
dc.subjectAddress translationen_US
dc.titleHardware/software approaches for reducing the process variation impact on instruction fetchesen_US
dc.typeArticleen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage54:1en_US
dc.citation.epage54:23en_US
dc.citation.volumeNumber18en_US
dc.citation.issueNumber4en_US
dc.identifier.doi10.1145/2489778en_US
dc.publisherACM New York, NYen_US


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