In this thesis, a new method for the design of tunable current-mode CMOS filters is presented. The proposed structure is suitable for low-voltage (3V) and high frequency applications. Basic building blocks are differential damped integrator and differential damped differentiator, which have tunable comer frequencies. Using first order building blocks and applying feedback techniques, biquadratic sections of low-pass, high-pass and band-pass filters are generated. Higher order filters are implemented by using cascaded biquad synthesis. Filters are tuned by means of two control voltages, from 50% to 130% of their corner frequencies. HSPICE simulations show that filter implementation up to 0.5GHz is possible for 2.4^ CMOS technology. The available frequency range can be increased using a better technology such as 0.7/i CMOS. Layouts for two test chips are generated using CADENCE full-custom design environment for 0.7/i and 2.4/i CMOS processes.