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    Adaptive thread and memory access schelduling in chip multiprocessors

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    Date Issued
    2013
    Author
    Aktürk, İsmail
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    Please cite this item using this persistent URL
    http://hdl.handle.net/11693/15856
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    • Dept. of Computer Engineering - Master's degree [446]
    Advisor
    Öztürk, Özcan
    Publisher
    Bilkent University
    Abstract
    The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers used in operating systems, and thread-oblivious memory access schedulers used in off-chip main memory controllers. For the thread scheduling, we introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized. A novel multi-metric scoring scheme is used that specifies the L1 cache access characteristics of a thread. The scheduling decisions are made based on multi-metric scores of threads. For the memory access scheduling, we introduce an adaptive compute-phase prediction and thread prioritization scheme that efficiently categorize threads based on execution characteristics and provides fine-grained prioritization that allows to differentiate threads and prioritize their memory access requests accordingly.

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    BİLKENT UNIVERSITY

    Copyright © Bilkent University - Library Technical Services | 06800 Bilkent, Ankara TURKEY
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