An execution triggered coarse grained recongigurable architecture
Author
Atak, Oğuzhan
Advisor
Atalar, Abdullah
Date
2012Publisher
Bilkent University
Language
English
Type
ThesisItem Usage Stats
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Abstract
In this thesis, we present BilRC (Bilkent Reconfigurable Computer), a new
coarse-grained reconfigurable architecture. The distinguishing feature of BilRC
is its novel execution-triggering computation model which allows a broad range
of applications to be efficiently implemented. In order to map applications onto
BilRC, we developed a control data flow graph language, named LRC (a Language
for Reconfigurable Computing). The flexibility of the architecture and
the computation model are validated by mapping several real world applications.
LRC is also used to map applications to a 90nm FPGA, giving exactly the same
cycle count performance. It is found that BilRC reduces the configuration size
about 33 times. It is synthesized with 90nm technology and typical applications
mapped on BilRC run about 2.5 times faster than those on FPGA. It is found
that the cycle counts of the applications for a commercial VLIW DSP processor
are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can
run the inverse discrete cosine transform algorithm almost 3 times faster than
the closest CGRA in terms of cycle count. Although the area required for BilRC
processing elements is larger than that of existing CGRAs, this is mainly due to
the segmented interconnect architecture of BilRC, which is crucial for supporting
a broad range of applications.
Keywords
Coarse-grained Reconfigurable Architectures (CGRA)Discrete Cosine Transform (DCT)
Viterbi Decoder
Turbo Decoder
Fast Fourier Transform (FFT)
Reconfigurable Computing
Field Programmable Gate Arrays (FPGA)