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    Self-aligning planarization and passivation for integration applications in III-V semiconductor devices

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    10.1109-TSM.2004.841834.pdf (1.965Mb)
    Date Issued
    2005
    Author
    Demir, H. V.
    Zheng, J. F.
    Sabnis, V. A.
    Fidaner, O.
    Hanberg, J. P.
    Harris, J. S.
    Miller, D. A. B.
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    Please cite this item using this persistent URL
    http://hdl.handle.net/11693/11462
    Journal
    IEEE Transactions on Semiconductor Manufacturing
    Published as
    http://dx.doi.org/10.1109/TSM.2004.841834
    Collections
    • Department of Physics [621]
    • Department of Electrical and Electronics Engineering [979]
    • Institute of Materials Science and Nanotechnology [306]
    Publisher
    IEEE
    Abstract
    This paper reports an easy planarization and passivation approach for the integration of III-V semiconductor devices. Vertically etched III-V semiconductor devices typically require sidewall passivation to suppress leakage currents and planarization of the passivation material for metal interconnection and device integration. It is, however, challenging to planarize all devices at once. This technique offers wafer-scale passivation and planarization that is automatically leveled to the device top in the 1-3-mum vicinity surrounding each device. In this method, a dielectric hard mask is used to define the device area. An undercut structure is intentionally created below the hard mask, which is retained during the subsequent polymer spinning and anisotropic polymer etch back., The spin-on polymer that fills in the undercut seals the sidewalls for all the devices across the wafer. After the polymer etch back, the dielectric mask is removed leaving the polymer surrounding each device level with its device top to atomic scale flatness. This integration method is robust and is insensitive to spin-on polymer thickness, polymer etch nonuniformity, and device height difference. It prevents the polymer under the hard mask from etch-induced damage and creates a polymer-free device surface for metallization upon removal of the dielectric mask. We applied this integration technique in fabricating an InP-based photonic switch that consists of a mesa photodiode and a quantum-well waveguide modulator using benzocyclobutene (BCB) polymer. We demonstrated functional integrated photonic switches with high process yield of >90%, high breakdown voltage of >25 V, and low ohmic contact resistance of similar to 10 Omega. To the best of our knowledge, such an integration of a surface-normal photodiode and a lumped electroabsorption modulator with the use of BCB is the first to be implemented on a single substrate.
    Citation
    Demir, H. V., Zheng, J. F., Sabnis, V. A., Fidaner, O., Hanberg, J., Harris, J. S., & Miller, D. A. (2005). Self-aligning planarization and passivation for integration applications in III-V semiconductor devices. Semiconductor Manufacturing, IEEE Transactions on, 18(1), 182-189.

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    BİLKENT UNIVERSITY

    Copyright © Bilkent University - Library Technical Services | 06800 Bilkent, Ankara TURKEY
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