Browsing by Subject "Digital storage"
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Item Open Access Automatic tag expansion using visual similarity for photo sharing websites(Springer New York LLC, 2010) Sevil, S. G.; Kucuktunc, O.; Duygulu, P.; Can, F.In this paper we present an automatic photo tag expansion method designed for photo sharing websites. The purpose of the method is to suggest tags that are relevant to the visual content of a given photo at upload time. Both textual and visual cues are used in the process of tag expansion. When a photo is to be uploaded, the system asks for a couple of initial tags from the user. The initial tags are used to retrieve relevant photos together with their tags. These photos are assumed to be potentially content related to the uploaded target photo. The tag sets of the relevant photos are used to form the candidate tag list, and visual similarities between the target photo and relevant photos are used to give weights to these candidate tags. Tags with the highest weights are suggested to the user. The method is applied on Flickr (http://www.flickr. com ). Results show that including visual information in the process of photo tagging increases accuracy with respect to text-based methods. © 2009 Springer Science+Business Media, LLC.Item Open Access Charge Trapping Memory with 2.85-nm Si-Nanoparticles Embedded in HfO2(ECS, 2015-05) El-Atab, N.; Turgut, Berk Berkan; Okyay, Ali Kemal; Nayfeh, A.In this work, the effect of embedding 2.85-nm Si-nanoparticles charge trapping layer in between double layers of high-κ Al2O3/HfO2 oxides is studied. Using high frequency (1 MHz) C-Vgate measurements, the memory showed a large memory window at low program/erase voltages due to the charging of the Si-nanoparticles. The analysis of the C-V characteristics shows that mixed charges are being stored in the Si-nanoparticles where electrons get stored during the program operation while holes dominate in the Si-nanoparticles during the erase operation. Moreover, the retention characteristic of the memory is studied by measuring the memory hysteresis in time. The obtained retention characteristic (35.5% charge loss in 10 years) is due to the large conduction and valence band offsets between the Si-nanoparticles and the Al2O3/HfO2 tunnel oxide. The results show that band engineering is essential in future low-power non-volatile memory devices. In addition, the results show that Si-nanoparticles are promising in memory applications.Item Open Access Classifying human leg motions with uniaxial piezoelectric gyroscopes(2009) Tunçel O.; Altun, K.; Barshan, B.This paper provides a comparative study on the different techniques of classifying human leg motions that are performed using two low-cost uniaxial piezoelectric gyroscopes worn on the leg. A number of feature sets, extracted from the raw inertial sensor data in different ways, are used in the classification process. The classification techniques implemented and compared in this study are: Bayesian decision making (BDM), a rule-based algorithm (RBA) or decision tree, least-squares method (LSM), k-nearest neighbor algorithm (k-NN), dynamic time warping (DTW), support vector machines (SVM), and artificial neural networks (ANN). A performance comparison of these classification techniques is provided in terms of their correct differentiation rates, confusion matrices, computational cost, and training and storage requirements. Three different cross-validation techniques are employed to validate the classifiers. The results indicate that BDM, in general, results in the highest correct classification rate with relatively small computational cost. © 2009 by the authors.Item Open Access Continuous mesoporous pd films by electrochemical deposition in nonionic micellar solution(American Chemical Society, 2017) Iqbal, M.; Li C.; Wood, K.; Jiang B.; Takei, T.; Dag, Ö.; Baba, D.; Nugraha, A. S.; Asahi, T.; Whitten, A. E.; Hossain, M. S. A.; Malgras, V.; Yamauchi, Y.Mesoporous metals that combine catalytic activity and high surface area can provide more opportunities for electrochemical applications. Various synthetic methods, including hard and soft templating, have been developed to prepare mesoporous/nanoporous metals. Micelle assembly, typically involved in soft-templates, is flexible and convenient for such purposes. It is, however, difficult to control, and the ordering is significantly destroyed during the metal deposition process, which is detrimental when it comes to designing precisely mesostructured materials. In the present work, mesoporous Pd films were uniformly electrodeposited using a nonionic surfactant, triblock copolymer poly(ethylene oxide)-b-poly(propylene oxide)-b-poly(ethylene oxide), as a pore-directing agent. The interaction between micelles and metal precursors greatly influences the metal growth and determines the final structure. The water-coordinated species interact with the ethylene oxide moiety of the micelles to effectively drive the Pd(II) species toward the working electrode surface. From small-angle neutron scattering data, it is found that spherical P123 micelles, with an average diameter of ∼14 nm, are formed in the electrolyte, and the addition of Pd ions does not significantly modify their structure, which is the essence of the micelle assembly approach. The uniformly sized mesopores are formed over the entire mesoporous Pd film and have an average pore diameter of 10.9 nm. Cross-sectional observation of the film also shows mesopores spanning continuously from the bottom to the top of the film. The crystallinity, crystal phase, and electronic coordination state of the Pd film are also confirmed. Through this study, it is found that the optimized surfactant concentration and applied deposition potential are the key factors to govern the formation of homogeneous and well-distributed pores over the entire film. Interestingly, the as-prepared mesoporous Pd films exhibit superior electrocatalytic activity toward the ethanol oxidation reaction by fully utilizing the accessible active surface area. Our approach combines electrochemistry with colloidal and coordination chemistry and is widely applicable to other promising metals and alloy electrocatalysts.Item Open Access Distributed block formation and layout for disk-based management of large-scale graphs(Springer, 2017) Yaşar, A.; Gedik, B.; Ferhatosmanoğlu, H.We are witnessing an enormous growth in social networks as well as in the volume of data generated by them. An important portion of this data is in the form of graphs. In recent years, several graph processing and management systems emerged to handle large-scale graphs. The primary goal of these systems is to run graph algorithms and queries in an efficient and scalable manner. Unlike relational data, graphs are semi-structured in nature. Thus, storing and accessing graph data using secondary storage requires new solutions that can provide locality of access for graph processing workloads. In this work, we propose a scalable block formation and layout technique for graphs, which aims at reducing the I/O cost of disk-based graph processing algorithms. To achieve this, we designed a scalable MapReduce-style method called ICBL, which can divide the graph into a series of disk blocks that contain sub-graphs with high locality. Furthermore, ICBL can order the resulting blocks on disk to further reduce non-local accesses. We experimentally evaluated ICBL to showcase its scalability, layout quality, as well as the effectiveness of automatic parameter tuning for ICBL. We deployed the graph layouts generated by ICBL on the Neo4j open source graph database, http://www.neo4j.org/ (2015) graph database management system. Our results show that the layout generated by ICBL reduces the query running times over Neo4j more than 2 × compared to the default layout. © 2017, Springer Science+Business Media New York.Item Open Access Effects of cognitive styles on 2D drafting and design performance in digital media(Springer Netherlands, 2010) Pektas, S.T.This paper investigates the interactions between design students' cognitive styles, as measured by Riding's Cognitive Styles Analysis, and performance in 2D drafting and design tasks in digital media. An empirical research revealed that Imager students outperformed Verbalisers in both drafting and creativity scores. Wholist-Analytic cognitive style dimension was found to be independent from drafting and design performance. The study suggests that examining the cognitive styles of students in Computer Aided Design (CAD) education deserves further attention and may facilitate for improvements in learning processes. © 2008 Springer Science+Business Media B.V.Item Open Access Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O3/HfO2 tunnel oxide(Springer New York LLC, 2015) El-Atab, N.; Turgut, B. B.; Okyay, Ali Kemal; Nayfeh, M.; Nayfeh, A.In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.Item Open Access GenoGuard: protecting genomic data against brute-force attacks(IEEE, 2015-05) Huang, Z.; Ayday, Erman; Fellay, Jacques; Hubaux, J-P.; Juels, A.Secure storage of genomic data is of great and increasing importance. The scientific community's improving ability to interpret individuals' genetic materials and the growing size of genetic database populations have been aggravating the potential consequences of data breaches. The prevalent use of passwords to generate encryption keys thus poses an especially serious problem when applied to genetic data. Weak passwords can jeopardize genetic data in the short term, but given the multi-decade lifespan of genetic data, even the use of strong passwords with conventional encryption can lead to compromise. We present a tool, called Geno Guard, for providing strong protection for genomic data both today and in the long term. Geno Guard incorporates a new theoretical framework for encryption called honey encryption (HE): it can provide information-theoretic confidentiality guarantees for encrypted data. Previously proposed HE schemes, however, can be applied to messages from, unfortunately, a very restricted set of probability distributions. Therefore, Geno Guard addresses the open problem of applying HE techniques to the highly non-uniform probability distributions that characterize sequences of genetic data. In Geno Guard, a potential adversary can attempt exhaustively to guess keys or passwords and decrypt via a brute-force attack. We prove that decryption under any key will yield a plausible genome sequence, and that Geno Guard offers an information-theoretic security guarantee against message-recovery attacks. We also explore attacks that use side information. Finally, we present an efficient and parallelized software implementation of Geno Guard. © 2015 IEEE.Item Open Access Graphene Nanoplatelets Embedded in HfO2 for MOS Memory(Electrochemical Society Inc., 2015) El-Atab, N.; Turgut, Berk Berkan; Okyay, Ali Kemal; Nayfeh, A.In this work, a MOS memory with graphene nanoplatelets charge trapping layer and a double layer high-κ Al2O3/HfO2 tunnel oxide is demonstrated. Using C-Vgate measurements, the memory showed a large memory window at low program/erase voltages. The analysis of the C-V characteristics shows that electrons are being stored in the graphene-nanoplatelets during the program operation. In addition, the retention characteristic of the memory is studied by plotting the hysteresis measurement vs. time. The measured excellent retention characteristic (28.8% charge loss in 10 years) is due to the large electron affinity of the graphene. The analysis of the plot of the energy band diagram of the MOS structure further proves its good retention characteristic. Finally, the results show that such graphene nanoplatelets are promising in future low-power non-volatile memory devices.Item Open Access A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors(IEEE, 2016-05) Asad, Arghavan; Onsori, Salman; Fathy, M.; Jahed-Motlagh, M. R.; Raahemifar, K.Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system for 3D chip-multiprocessors to take advantages of both traditional and non-volatile memory technologies. For reaching this target, we present a convex optimization-based model that minimizes the system energy consumption while satisfy endurance constraint in order to design a reliable memory system. Experimental results show that the proposed method improves energy-delay product (EDP) and performance by about 44.8% and 13.8% on average respectively compared with the traditional memory design where single technology is used. © 2016 IEEE.Item Open Access High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model(IEEE, 2016-05) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE.Item Open Access A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model(IEEE, 2015-11) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE.Item Open Access Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach(IEEE, 2015-12) Onsori, Salman; Asad, A.; Öztürk, Özcan; Fathy, M.Energy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue for embedded systems. Using conventional memory technologies in future designs in nano-scale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies are promising replacement for conventional memory structure in embedded systems due to its attractive characteristics such as near-zero leakage power, high density and non-volatility. Recent advantages of NVM technologies can significantly mitigate the issue of memory leakage power. However, they introduce new challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system to minimize energy consumption for 3D embedded chip-multiprocessors (eCMP). For reaching this target, we present a convex optimization-based model to distribute data blocks between SRAM and NVM banks based on data access pattern derived by compiler. Our compiler-assisted hybrid memory architecture can achieve up to 51.28 times improvement in lifetime. In addition, experimental results show that our proposed method reduce energy consumption by 56% on average compared to the traditional memory design where single technology is used. © 2015 IEEE.Item Open Access Implications of non-volatile memory as primary storage for database management systems(IEEE, 2017) Mustafa, Naveed Ul; Armejach, A.; Öztürk, Özcan; Cristal, A.; Unsal, O. S.Traditional Database Management System (DBMS) software relies on hard disks for storing relational data. Hard disks are cheap, persistent, and offer huge storage capacities. However, data retrieval latency for hard disks is extremely high. To hide this latency, DRAM is used as an intermediate storage. DRAM is significantly faster than disk, but deployed in smaller capacities due to cost and power constraints, and without the necessary persistency feature that disks have. Non-Volatile Memory (NVM) is an emerging storage class technology which promises the best of both worlds. It can offer large storage capacities, due to better scaling and cost metrics than DRAM, and is non-volatile (persistent) like hard disks. At the same time, its data retrieval time is much lower than that of hard disks and it is also byte-addressable like DRAM. In this paper, we explore the implications of employing NVM as primary storage for DBMS. In other words, we investigate the modifications necessary to be applied on a traditional relational DBMS to take advantage of NVM features. As a case study, we have modified the storage engine (SE) of PostgreSQL enabling efficient use of NVM hardware. We detail the necessary changes and challenges such modifications entail and evaluate them using a comprehensive emulation platform. Results indicate that our modified SE reduces query execution time by up to 40% and 14.4% when compared to disk and NVM storage, with average reductions of 20.5% and 4.5%, respectively. © 2016 IEEE.Item Open Access Memory effect by charging of ultra‐small 2‐nm laser‐synthesized solution processable Si‐nanoparticles embedded in Si–Al2O3–SiO2 structure(Wiley-VCH Verlag, 2015) El-Atab, N.; Rizk, A.; Tekcan, B.; Alkis, S.; Okyay, Ali Kemal; Nayfeh, A.A memory structure containing ultra-small 2-nm laser-synthesized silicon nanoparticles is demonstrated. The Si-nanoparticles are embedded between an atomic layer deposited high-κ dielectric Al2O3 layer and a sputtered SiO2 layer. A memory effect due to charging of the Si nanoparticles is observed using high frequency C-V measurements. The shift of the threshold voltage obtained from the hysteresis measurements is around 3.3V at 10/-10V gate voltage sweeping. The analysis of the energy band diagram of the memory structure and the negative shift of the programmed C-V curve indicate that holes are tunneling from p-type Si via Fowler-Nordheim tunneling and are being trapped in the Si nanoparticles. In addition, the structures show good endurance characteristic (>105program/erase cycles) and long retention time (>10 years), which make them promising for applications in non-volatile memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.Item Open Access NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories(IEEE, 2016-08-09) Alouani, I.; Ahangari, Hamzeh; Öztürk, Özcan; Niar, S.Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to enhance error resilience of SRAMs by exploiting the adjacent memory bit data. Bit cells of a memory line are paired together in circuit level to mutually increase the static noise margin and critical charge of a cell. Unlike existing techniques, NS-SRAM aims to enhance both Bit Error Rate (BER) and Soft Error rate (SER) at the same time. Due to auto-adaptive joiners, each of the adjacent cells' nodes is connected to its counterpart in the neighbor bit. NS-SRAM enhances read-stability by increasing critical Read Static Noise Margin (RSNM), thereby decreasing faults when circuit operates under voltage scaling. It also increases hold-stability and critical charge to mitigate soft-errors. By the proposed technique, reliability of SRAM based structures such as cache memories and register files can drastically be improved with comparable area overhead to existing hardening techniques. Moreover it does not require any extra-memory, does not impact the memory effective size, and has no negative impact on performance. © 2016 IEEE.Item Open Access Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy(Elsevier BV, 2017) Asad, A.; Ozturk, O.; Fathy, M.; Jahed-Motlagh, M. R.Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, addressing dark silicon challenges in uncore component designs such as cache hierarchy, on-chip interconnect etc. that consume significant portion of the on-chip power consumption is largely unexplored. In this paper, for the first time, we propose an integrated approach which considers the impact of power consumption of core and uncore components simultaneously to improve multi/many-core performance in the dark silicon era. The proposed approach dynamically (1) predicts the changing program behavior on each core; (2) re-determines frequency/voltage, cache capacity and technology in each level of the cache hierarchy based on the program's scalability in order to satisfy the power and temperature constraints. In the proposed architecture, for future chip-multiprocessors (CMPs), we exploit emerging technologies such as non-volatile memories (NVMs) and 3D techniques to combat dark silicon. Also, for the first time, we propose a detailed power model which is useful for future dark silicon CMPs power modeling. Experimental results on SPEC 2000/2006 benchmarks show that the proposed method improves throughput by about 54.3% and energy-delay product by about 61% on average, respectively, in comparison with the conventional CMP architecture with homogenous cache system. (A preliminary short version of this work was presented in the 18th Euromicro Conference on Digital System Design (DSD), 2015.) © 2017 Elsevier B.V.Item Open Access OptMem: dark-silicon aware low latency hybrid memory design(IEEE, 2016-01) Onsori, Salman; Asad, Arghavan A; Raahemifar, K.; Fathy, M.In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-Transfer torque magnetic random-Access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design. © 2016 IEEE.Item Open Access A privacy-preserving solution for the bipartite ranking problem(IEEE, 2016-12) Faramarzi, Noushin Salek; Ayday, Erman; Güvenir, H. AltayIn this paper, we propose an efficient solution for the privacy-preserving of a bipartite ranking algorithm. The bipartite ranking problem can be considered as finding a function that ranks positive instances (in a dataset) higher than the negative ones. However, one common concern for all the existing schemes is the privacy of individuals in the dataset. That is, one (e.g., a researcher) needs to access the records of all individuals in the dataset in order to run the algorithm. This privacy concern puts limitations on the use of sensitive personal data for such analysis. The RIMARC (Ranking Instances by Maximizing Area under the ROC Curve) algorithm solves the bipartite ranking problem by learning a model to rank instances. As part of the model, it learns weights for each feature by analyzing the area under receiver operating characteristic (ROC) curve. RIMARC algorithm is shown to be more accurate and efficient than its counterparts. Thus, we use this algorithm as a building-block and provide a privacy-preserving version of the RIMARC algorithm using homomorphic encryption and secure multi-party computation. Our proposed algorithm lets a data owner outsource the storage and processing of its encrypted dataset to a semi-trusted cloud. Then, a researcher can get the results of his/her queries (to learn the ranking function) on the dataset by interacting with the cloud. During this process, neither the researcher nor the cloud learns any information about the raw dataset. We prove the security of the proposed algorithm and show its efficiency via experiments on real data.Item Open Access RailwayDB: adaptive storage of interaction graphs(Association for Computing Machinery, 2016) Soulé R.; Gedik, B.We are living in an ever more connected world, where data recording the interactions between people, software systems, and the physical world is becoming increasingly prevalent. These data often take the form of a temporally evolving graph, where entities are the vertices and the interactions between them are the edges. We call such graphs interaction graphs. Various domains, including telecommunications, transportation, and social media, depend on analytics performed on interaction graphs. The ability to efficiently support historical analysis over interaction graphs requires effective solutions for the problem of data layout on disk. This paper presents an adaptive disk layout called the railway layout for optimizing disk block storage for interaction graphs. The key idea is to divide blocks into one or more sub-blocks. Each sub-block contains the entire graph structure, but only a subset of the attributes. This improves query I/O, at the cost of increased storage overhead. We introduce optimal integer linear program (ILP) formulations for partitioning disk blocks into sub-blocks with overlapping and nonoverlapping attributes. Additionally, we present greedy heuristics that can scale better compared to the ILP alternatives, yet achieve close to optimal query I/O. We provide an implementation of the railway layout as part of RailwayDB—an open-source graph database we have developed. To demonstrate the benefits of the railway layout, we provide an extensive experimental evaluation, including model-based as well as empirical results comparing our approach to baseline alternatives.