Browsing by Author "Kim, T."
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Item Open Access Ag@SiO2-embedded InGaN/GaN nanorod array white light-emitting diode with perovskite nanocrystal films(Elsevier, 2021-10-28) Shin, Do-Y.; Kim, T.; Akyüz, Özgün; Demir, Hilmi Volkan; Lee, In-H.White light-emitting diodes (LEDs) are great candidates for general lighting. Phosphors have commonly been used for the color conversion layers of white LEDs; however, they backscatter more than half of the down-converted light, which is lost within the device, thus degrading the overall performance. In this study, we propose and demonstrate white LEDs with improved efficiency enabled by the intimate integration of Ag@SiO2-supported blue InGaN/GaN nanorod LEDs together with green- and red-emitting perovskite nanocrystal (PNC) films as color conversion layers. The photoluminescence (PL) intensity of the blue LEDs (BLEDs) was significantly enhanced owing to the localized surface plasmon (LSP) effect of Ag@SiO2 nanoparticles. In addition, the perovskite PL intensity was improved by the high-power BLED backlight. The resulting PL intensity of the Ag@SiO2 nanoparticle-embedded nanorod white LED was 62% greater than that of a planar white LED.Item Open Access Architectural requirements for energy efficient execution of graph analytics applications(IEEE, 2015-11) Özdal, Muhammet Mustafa; Yeşil, Şerif; Kim, T.; Ayupov, A.; Burns, S.; Öztürk, ÖzcanIntelligent data analysis has become more important in the last decade especially because of the significant increase in the size and availability of data. In this paper, we focus on the common execution models and characteristics of iterative graph analytics applications. We show that the features that improve work efficiency can lead to significant overheads on existing systems. We identify the opportunities for custom hardware implementation, and outline the desired architectural features for energy efficient computation of graph analytics applications. © 2015 IEEE.Item Open Access Energy efficient architecture for graph analytics accelerators(IEEE, 2016-06) Özdal, Muhammet Mustafa; Yeşil, Şerif; Kim, T.; Ayupov, A.; Greth, J.; Burns, S.; Öztürk, ÖzcanSpecialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications. The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. In our experiments, we study several graph-parallel applications, and show that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance. We also estimate the area requirement and power consumption of these hardware accelerators through physical-aware logic synthesis, and show up to 65x better power consumption with significantly smaller area. © 2016 IEEE.Item Open Access Graph analytics accelerators for cognitive systems(Institute of Electrical and Electronics Engineers, 2017) Ozdal, M. M.; Yesil, S.; Kim, T.; Ayupov, A.; Greth, J.; Burns, S.; Ozturk, O.Hardware accelerators are known to be performance and power efficient. This article focuses on accelerator design for graph analytics applications, which are commonly used kernels for cognitive systems. The authors propose a templatized architecture that is specifically optimized for vertex-centric graph applications with irregular memory access patterns, asynchronous execution, and asymmetric convergence. The proposed architecture addresses the limitations of existing CPU and GPU systems while providing a customizable template. The authors' experiments show that the generated accelerators can outperform a high-end CPU system with up to 3 times better performance and 65 times better power efficiency. © 1981-2012 IEEE.Item Open Access Hardware accelerator design for data centers(IEEE, 2016-11) Yeşil, Şerif; Özdal, Muhammet Mustafa; Kim, T.; Ayupov, A.; Burns, S.; Öztürk, Özcan.As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized application-specific accelerators are becoming integral parts of modern system on chip (SOC) architectures. In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs. © 2015 IEEE.Item Open Access A template-based design methodology for graph-parallel hardware accelerators(IEEE, 2017-05) Ayupov, A.; Yeşil, Şerif; Özdal, Muhammet Mustafa; Kim, T.; Burns, S.; Öztürk, ÖzcanGraph applications have been gaining importance in the last decade due to emerging big data analytics problems such as Web graphs, social networks, and biological networks. For these applications, traditional CPU and GPU architectures suffer in terms of performance and power consumption due to irregular communications, random memory accesses, and load balancing problems. It has been shown that specialized hardware accelerators can achieve much better power and energy efficiency compared to the general purpose CPUs and GPUs. In this paper, we present a template-based methodology specifically targeted for hardware accelerator design of big-data graph applications. Important architectural features that are key for energy efficient execution are implemented in a common template. The proposed template-based methodology is used to design hardware accelerators for different graph applications with little effort. Compared to an application-specific high-level synthesis methodology, we show that the proposed methodology can generate hardware accelerators with up to 18× better energy efficiency and requires less design effort.Item Open Access X‐Space MPI: magnetic nanoparticles for safe medical imaging(Wiley, 2012) Goodwill, P.; Sarıtaş, Emine Ülkü; Croft, L.; Kim, T.; Krishnan, K.; Schaffer, D.; Conolly, S.One quarter of all iodinated contrast X‐ray clinical imaging studies are now performed on Chronic Kidney Disease (CKD) patients. Unfortunately, the iodine contrast agent used in X‐ray is often toxic to CKD patients’ weak kidneys, leading to significant morbidity and mortality. Hence, we are pioneering a new medical imaging method, called Magnetic Particle Imaging (MPI), to replace X‐ray and CT iodinated angiography, especially for CKD patients. MPI uses magnetic nanoparticle contrast agents that are much safer than iodine for CKD patients. MPI already offers superb contrast and extraordinary sensitivity. The iron oxide nanoparticle tracers required for MPI are also used in MRI, and some are already approved for human use, but the contrast agents are far more effective at illuminating blood vessels when used in the MPI modality. We have recently developed a systems theoretic framework for MPI called x‐space MPI, which has already dramatically improved the speed and robustness of MPI image reconstruction. X‐space MPI has allowed us to optimize the hardware for five MPI scanners. Moreover, x‐space MPI provides a powerful framework for optimizing the size and magnetic properties of the iron oxide nanoparticle tracers used in MPI. Currently MPI nanoparticles have diameters in the 10‐20 nanometer range, enabling millimeter‐scale resolution in small animals. X‐space MPI theory predicts that larger nanoparticles could enable up to 250 micrometer resolution imaging, which would represent a major breakthrough in safe imaging for CKD patients.