Browsing by Keywords "Systems analysis"

Adaptive prefetching for shared cache based chip multiprocessors

Kandemir, M.; Zhang, Y.; Öztürk, Özcan (IEEE, 2009-04)

Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip ...

Analysis of assembly systems for interdeparture time variability and throughput

Sabuncuoğlu, İ.; Erel, E.; Kok, A. G. (Taylor & Francis, 2002)

This paper studies the effect of the number of component stations (parallelism), work transfer, processing time distributions, buffers and buffer allocation schemes on throughput and interdeparture time variability of ...

Analysis of design parameters in SIL-4 safety-critical computer

Ahangari, Hamzeh; Özkök, Y. I.; Yıldırım, A.; Say, F.; Atik, Funda; Öztürk, Özcan (IEEE, 2017-01)

Nowadays, Safety-critical computers are extensively used in may civil domains like transportation including railways, avionics and automotive. We noticed that in design of some previous works, some critical safety design ...

Auction based scheduling for distributed systems

Zarifoğlu, Emrah; Sabuncuoğlu, İhsan (International Institute of Informatics and Systemics, 2006)

Businesses deal with huge databases over a geographically distributed supply network. When this is combined with scheduling and planning needs, it becomes too difficult to handle. Recently, Fast Consumer Goods sector tends ...

Cellular manufacturing system design using a holonistic approach

Aktürk, M. S.; Türkcan, A. (Taylor & Francis, 2000)

We propose an integrated algorithm that will solve the part-family and machine-cell formation problem by simultaneously considering the within-cell layout problem. To the best of our knowledge, this is the first study that ...

Code scheduling for optimizing parallelism and data locality

Yemliha, T.; Kandemir, M.; Öztürk, Özcan; Kultursay, E.; Muralidhara, S. P. (Springer, 2010-08-09)

As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ...

Distributed interactive video system design and analysis

Wu, Tsong-Ho; Korpeoglu, I.; Cheng, Bo-Chao (Institute of Electrical and Electronics Engineers, 1997)

The interactive video (IV) market has been expected to capture a significant share of the huge potential revenues to be generated by the business and residential markets. The level of revenues generated depends on the ...

The fractional Fourier domain decomposition

Kutay, M. A.; Özaktaş, H.; Özaktaş, Haldun M.; Arıkan, Orhan (Elsevier, 1999)

We introduce the fractional Fourier domain decomposition. A procedure called pruning, analogous to truncation of the singular-value decomposition, underlies a number of potential applications, among which we discuss fast ...

Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach

Onsori, Salman; Asad, A.; Öztürk, Özcan; Fathy, M. (IEEE, 2015-12)

Energy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue ...

Interaction of design and operational parameters in periodic review kanban systems

Erhun, F.; Aktürk, M. S.; Türkcan, A. (Taylor & Francis, 2003)

In this study, we propose an analytical model to determine the withdrawal cycle length, kanban sizes and number of kanbans simultaneously in a multi-item, multi-stage, multi-period, capacitated periodic review kanban system. ...

Market-driven approach based on Markov decision theory for optimal use of resources in software development

Noppen, J.; Aksit, M.; Nicola, V.; Tekinerdogan, B. (Institution of Engineering and Technology, 2004)

Changes in requirements may have a severe impact on development processes. For example, if requirements change during the course of a software development activity, it may be necessary to reschedule development activities ...

NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories

Alouani, I.; Ahangari, Hamzeh; Öztürk, Özcan; Niar, S. (IEEE, 2016-08-09)

Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to ...

On the design of dynamic associative neural memories

Savran, M. E.; Morgül, Ö. (IEEE, 1994)

We consider the design problem for a class of discrete-time and continuous-time neural networks. We obtain a characterization of all connection weights that store a given set of vectors into the network; that is, each given ...

On-chip memory space partitioning for chip multiprocessors using polyhedral algebra

Ozturk, O.; Kandemir, M.; Irwin, M. J. (The Institution of Engineering and Technology, 2010)

One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the ...

Online solutions for scalable file server systems

Tse, Savio S. H. (ACM, 2006)

We propose three online algorithms for scalable file server systems. A scalable file server is expected to provide rather stable services while the numbers of users, tasks, and data volumes keep increasing. One of the ...

Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy

Asad, A.; Ozturk, O.; Fathy, M.; Jahed-Motlagh, M. R. (Elsevier BV, 2017)

Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, ...