Browsing by Keywords "Signal Integrity"
Now showing items 1-2 of 2
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An ILP formulation for application mapping onto Network-on-Chips
(IEEE, 2009)Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems ... -
Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect
(IEEE, 2013)Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this ...