Now showing items 1-2 of 2

    • Analysis of scratch-pad memory-based processor architecture for graph applications 

      Saeed, Muhammad Aamir (Bilkent University, 2021-09)
      In graph analytic applications, main memory accesses prove to be a bottleneck as graphs have a poor spatial and temporal locality usage in the caches and higher memory hierarchy. Although this bottleneck is slightly ...
    • A scratch-pad memory aware dynamic loop scheduling algorithm 

      Öztürk, Özcan; Kandemir, M.; Narayanan, S. H. K. (IEEE, 2008-03)
      Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, ...