Browsing by Keywords "Random access storage"
Now showing items 1-6 of 6
-
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
(IEEE, 2016-05)In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and ... -
A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model
(IEEE, 2015-11)In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories ... -
Memory resident parallel inverted index construction
(Springer, London, 2012)Advances in cloud computing, 64-bit architectures and huge RAMs enable performing many search related tasks in memory.We argue that term-based partitioned parallel inverted index construction is among such tasks, and provide ... -
NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories
(IEEE, 2016-08-09)Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to ... -
OptMem: dark-silicon aware low latency hybrid memory design
(IEEE, 2016-01)In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static ... -
A two phase successive cancellation decoder architecture for polar codes
(IEEE, 2013)We propose a two-phase successive cancellation (TPSC) decoder architecture for polar codes that exploits the array-code property of polar codes by breaking the decoding of a length-TV polar code into a series of length-√ ...
