Browsing by Keywords "Network-on-chip"

Now showing items 1-6 of 6

    • Adaptive routing framework for network on chip architectures 

      Mustafa, N. U.; Ozturk, O.; Niar, S. (Association for Computing Machinery, 2016)
      In this paper we suggest and demonstrate the idea of applying multiple routing algorithms during the execution of a real application mapped on a Network-on-Chip (NoC). Traffic pattern of a real application may change during ...

    • Energy reduction in 3D NoCs through communication optimization 

      Ozturk, O.; Akturk I.; Kadayif I.; Tosun, S. (Springer Wien, 2015)
      Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining ...

    • Fault-tolerant irregular topology design method for network-on-chips 

      Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2014)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...

    • FPGA implementation of a fault-tolerant application-specific NoC design 

      Yesil, S.; Tosun, S.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2016)
      Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem ...

    • Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy 

      Asad, A.; Ozturk, O.; Fathy, M.; Jahed-Motlagh, M. R. (Elsevier BV, 2017)
      Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, ...

    • Voltage island based heterogeneous NoC design through constraint programming 

      Demiriz, A.; Bagherzadeh, N.; Ozturk, O. (Pergamon Press, 2014)
      This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior ...