Browsing by Keywords "Intel Xeon Phi"
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Exploiting locality in sparse matrixmatrix multiplication on manycore rchitectures
(IEEE Computer Society, 2017)Exploiting spatial and temporal localities is investigated for efficient rowbyrow parallelization of general sparse matrixmatrix multiplication (SpGEMM) operation of the form C=A,B on manycore architectures. Hypergraph ... 
Increasing data reuse in parallel sparse matrixvector and matrixtransposevector multiply on sharedmemory architectures
(Bilkent University, 2014)Sparse matrixvector and matrixtransposevector multiplications (Sparse AAT x) are the kernel operations used in iterative solvers. Sparsity pattern of the input matrix A, as well as its transpose, remains the same ... 
Localityaware parallel sparse matrixvector and matrixtransposevector multiplication on manycore processors
(Institute of Electrical and Electronics Engineers, 2016)Sparse matrixvector and matrixtransposevector multiplication (SpMMTV) repeatedly performed as z ← ATx and y ← A z (or y ← A w) for the same sparse matrix A is a kernel operation widely used in various iterative solvers. ... 
Parallel sparse matrix vector multiplication techniques for shared memory architectures
(Bilkent University, 2014)SpMxV (Sparse matrix vector multiplication) is a kernel operation in linear solvers in which a sparse matrix is multiplied with a dense vector repeatedly. Due to random memory access patterns exhibited by SpMxV operation, ... 
Spatiotemporal graph and hypergraph partitioning models for sparse matrixvector multiplication on manycore architectures
(IEEE Computer Society, 2019)There exist graph/hypergraph partitioningbased row/column reordering methods for encoding either spatial or temporal locality for sparse matrixvector multiplication (SpMV) operations. Spatial and temporal hypergraph ...