Now showing items 1-6 of 6

    • Fault-tolerant irregular topology design method for network-on-chips 

      Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2014)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
    • FPGA implementation of a fault-tolerant application-specific NoC design 

      Yesil, S.; Tosun, S.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2016)
      Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem ...
    • Hardware accelerator design for data centers 

      Yesil, S.; Ozdal, M. M.; Kim, T.; Ayupov, A.; Burns, S.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2016)
      As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized application-specific accelerators are becoming integral ...
    • Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy 

      Asad, A.; Ozturk, O.; Fathy, M.; Jahed-Motlagh, M. R. (Elsevier BV, 2017)
      Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, ...
    • OptMem: dark-silicon aware low latency hybrid memory design 

      Onsori, S.; Asad, A.; Raahemifar, K.; Fathy, M. (Institute of Electrical and Electronics Engineers Inc., 2016)
      In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static ...
    • Voltage island based heterogeneous NoC design through constraint programming 

      Demiriz, A.; Bagherzadeh, N.; Ozturk, O. (Pergamon Press, 2014)
      This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior ...